Hi,
Nice, thanks for figuring it out.
On Tue, Apr 1, 2014 at 9:58 AM, Tomi Valkeinen tomi.valkeinen@ti.com wrote:
I was able to get rid of the L3 errors when using TILER 2D buffer. Patch attached. It's illegal to use caching on TILER 2D buffers, so that was causing the issues.
Hmm, that was write combining, not caching. Shame even that doesn't work, accessing strongly ordered memory will be very slow even if the page fault problem is fixed.
It sucks having to use a shadow buffer, even if DMA does it, it still means additional ~1GB/s of memory bandwidth wasted (~500MB/s for reading + ~500MB/s for writing to TILER), which adds to ~500MB/s needed for DISPC to update the screen and whatever is needed for CPU to draw the frame. I hope ED makes the right decision and at least uses lower resolution screen.
GraÅžvydas