GPU: Difference between revisions
Jump to navigation
Jump to search
m (mentioned display) |
(Clarify GPU structure) |
||
| (3 intermediate revisions by one other user not shown) | |||
| Line 1: | Line 1: | ||
This is on the [[CPU-Board]], so has a chance of being upgraded in the future | <onlyinclude> | ||
This is on the [[CPU-Board]], as part of the OMAP5 SoC, so has a chance of being upgraded in the future | |||
but it cannot be changed separately to the CPU. Unlike a discrete GPU, each block reads/writes main system | |||
memory and final video output is done by the TI DISPC display controller block. | |||
*[http://www.imgtec.com/powervr/series5.asp PowerVR SGX SGX544-MP2] | *[http://www.imgtec.com/powervr/series5.asp PowerVR SGX SGX544-MP2] | ||
*[http://www.vivantecorp.com/en/technology/composition.html Vivante GC320] 2D Accelerator | *[http://www.vivantecorp.com/en/technology/composition.html Vivante GC320] 2D Accelerator | ||
*HDMI Encoder: HDMI 1.4a, HDCP 1.4, and DVI 1.0 Compliant" [http://www.ti.com/product/OMAP5432] | *HDMI Encoder: HDMI 1.4a, HDCP 1.4, and DVI 1.0 Compliant" [http://www.ti.com/product/OMAP5432]</onlyinclude> | ||
See also: | |||
See also: [[Display]] | *[[Display]] | ||
Latest revision as of 10:40, 22 June 2020
This is on the CPU-Board, as part of the OMAP5 SoC, so has a chance of being upgraded in the future but it cannot be changed separately to the CPU. Unlike a discrete GPU, each block reads/writes main system memory and final video output is done by the TI DISPC display controller block.
- PowerVR SGX SGX544-MP2
- Vivante GC320 2D Accelerator
- HDMI Encoder: HDMI 1.4a, HDCP 1.4, and DVI 1.0 Compliant" [1]
See also: