Hi,
I've talked to the memory distributor about our recent discoveries (DLL off, etc.) and got the following reply.
I hope my translation is correct (as the original was in German):
------------------------------
DLL Off only affects Reading. Dual Die Input cap is more critical regarding writing.
DLL Off means that the data will not be sent based on the clock...
Does the controller do an auto-training during power up or are you using fixed timing values?
With DLL off you should have a lot more issues than with DLL On... I've got no real explanation why a Dual Die should work better with DLL Off than on (except for if the timings aren't properly setup / trained).
A possibility could be that the termination is improperly for the Dual Die. A proper simulation with IBIS can only be done if the ODT Timings and values are known.
But if hardware leveling doesn't work with high temperatures, then it's probably more than just a bit of tuning...
But if DLL off works better than DLL on, it certainly looks like a timing issue, not a termination issue. I can run a simulation, but I'd need to know the timing which are being used to, for example, enable the ODT or the Receiver.
It's a fact that a dual die has a higher I/O capacitance. Swinging high and low will be reducing between the signal flanks.
Is there a reference design with two ranks (can also be two ranks with monolithic ICs) where one could grab the value of the termination resistors and capacitors around the chips?
------------------------
Two interesting things here: ODT Timings (they seem to be different depending on the chip used, have we checked those?)
And Termination. That's probably a question for Nikolaus: What resistors do we have here - and could those easily be changed for testing on a CPU board?
On 26 September 2017 at 12:41, Michael Mrozek EvilDragon@openpandora.org wrote:
Dual Die Input cap is more critical regarding writing.
Do they mean the power supply decoupling caps?
DLL Off means that the data will not be sent based on the clock...
Does the controller do an auto-training during power up?
Yup, which apparently suffices to compensate for the changes in read timing caused by DLL off. (Although possibly DLL-off timings might also be more prone to drift with temperature?)
With DLL off you should have a lot more issues than with DLL On... I've got no real explanation why a Dual Die should work better with DLL Off than on (except for if the timings aren't properly setup / trained).
I'm glad I'm not the only one puzzled by that.
A possibility could be that the termination is improper
The simulations juliano did seem to suggest signal integrity ought to be fine even without termination though.
A proper simulation with IBIS can only be done if the ODT Timings and values are known.
The values are known. I'm not 100% sure when exactly EMIF will assert the ODT signals though, I don't think I've ever seen this documented anywhere.
But if hardware leveling doesn't work with high temperatures, then it's probably more than just a bit of tuning...
Yup. To be fair, the hardware leveling done by EMIF has a history of being buggy and noise-sensitive. In earlier chips it was completely unusable and defeatured. On the other hand, I don't think I've ever seen a leveling failure on my 2GB cpu board, nor on the uEVM.
But if DLL off works better than DLL on, it certainly looks like a timing issue, not a termination issue.
Does DLL-off affect power consumption? (The simulation results for noise levels on VDD_DDR3 are still on my mind)
And Termination. That's probably a question for Nikolaus: What resistors do we have here - and could those easily be changed for testing on a CPU board?
There are no termination resistors other than those on-die (in omap and in memory). Discrete termination is normally only used for the command/address lines in a fly-by topology, whereas we're using a T-branch topology. See figure 7-48 "Floor Plan for the x16 DDR3 (T-Branch)" in section 7.7.2.4 "T-branch and Fly-by Topologies" of the OMAP5 public datasheet (SWPS051K).
Matthijs
Am 26.09.2017 um 15:25 schrieb Matthijs van Duin matthijsvanduin@gmail.com:
On 26 September 2017 at 12:41, Michael Mrozek EvilDragon@openpandora.org wrote:
Dual Die Input cap is more critical regarding writing.
Do they mean the power supply decoupling caps?
from context I think they refer to the capacity of each input (not power) pin (address, cs, data etc.) because that is the sum of two dies. Plus what the bonding wires can add. Our decoupling caps do not change.
This means we must drive more current into the wires so that these capacitors are charged/discharged faster. Or if we don't, they have a slower slope. Which means that the switching point from 0 to 1 or 1 to 0 is delayed in comparison to a single die ram package. Hence some signals arrive later.
What we don't know how big this effect is and which situation is really influenced.
And if *all* signals are slowed down y the same effect, it should compensate. Unless 0101 sequences become too fast. But we are far below max. RAM speed.
Apropos bonding: there could be more cross-talk inside the MCP than outside. I have no idea how these chips look like inside...
BTW: I have received another set of IM8G memory chip samples today and I hope I find time tomorrow to try to rework another CPU board.
Please cross fingers that the outcome is better and not another broken board (the one done previously has developed a short circuit on VDD-CORE which appears to be under or inside the OMAP5).
Otherwise we have to ask pick&place to build a handful of new CPU boards with these chips (eating more money and time).
BR, Nikolaus
Am 26.09.2017 um 12:41 schrieb Michael Mrozek EvilDragon@openpandora.org:
Hi,
I've talked to the memory distributor about our recent discoveries (DLL off, etc.) and got the following reply.
I hope my translation is correct (as the original was in German):
DLL Off only affects Reading. Dual Die Input cap is more critical regarding writing.
DLL Off means that the data will not be sent based on the clock...
Does the controller do an auto-training during power up or are you using fixed timing values?
With DLL off you should have a lot more issues than with DLL On... I've got no real explanation why a Dual Die should work better with DLL Off than on (except for if the timings aren't properly setup / trained).
A possibility could be that the termination is improperly for the Dual Die. A proper simulation with IBIS can only be done if the ODT Timings and values are known.
But if hardware leveling doesn't work with high temperatures, then it's probably more than just a bit of tuning...
But if DLL off works better than DLL on, it certainly looks like a timing issue, not a termination issue. I can run a simulation, but I'd need to know the timing which are being used to, for example, enable the ODT or the Receiver.
It's a fact that a dual die has a higher I/O capacitance. Swinging high and low will be reducing between the signal flanks.
Is there a reference design with two ranks (can also be two ranks with monolithic ICs) where one could grab the value of the termination resistors and capacitors around the chips?
Two interesting things here: ODT Timings (they seem to be different depending on the chip used, have we checked those?)
And Termination. That's probably a question for Nikolaus: What resistors do we have here - and could those easily be changed for testing on a CPU board?
Quick answer: they are inside the DDR3-Chips and the OMAP5. Not explicit components that we do design choose or install. Should IMHO be possible to program them by software in some range.
There are in total 8 external resistors with 240 Ohm at ZQ0 and ZQ1. Appears to be one for every chip (4 packages of 2 chips each).
Maybe this value must be changed? I don't know what they are really good for... The data sheet only references these 240 Ohm:
• Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω)
or
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
BR, Nikolaus
On 26 September 2017 at 17:09, H. Nikolaus Schaller hns@goldelico.com wrote:
There are in total 8 external resistors with 240 Ohm at ZQ0 and ZQ1. I don't know what they are really good for...
They're used to calibrate the impedance for the drivers and ODT (which would otherwise be rather imprecise and temperature-sensitive).
Matthijs
Am 26.09.2017 um 17:14 schrieb Matthijs van Duin matthijsvanduin@gmail.com:
On 26 September 2017 at 17:09, H. Nikolaus Schaller hns@goldelico.com wrote:
There are in total 8 external resistors with 240 Ohm at ZQ0 and ZQ1. I don't know what they are really good for...
They're used to calibrate the impedance for the drivers and ODT (which would otherwise be rather imprecise and temperature-sensitive).
Ok!
Do you think this can have an influcence?
BR, Nikolaus
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H. Nikolaus Schaller -
Matthijs van Duin -
Michael Mrozek