[PATCH v5 0/6] MIPS: CI20: Add efuse driver for Ingenic JZ4780 and attach to DM9000 for stable MAC addresses
* no longer RFC but PATCH * add yaml bindings (by Andreas Kemnade andreas@kemnade.info) * fixes to yaml (suggested by Rob Herring robh@kernel.org)
RFC V4 2020-02-17 17:55:35: * removed read_only for nvmem config because there is no write method * Kconfig: replaced depends MACH_JZ4780 with MACH_INGENIC * run through checkpatch and fixed issues * made use of devm_nvram_register() and get rid of jz4780_efuse_remove() (suggested by Srinivas Kandagatla srinivas.kandagatla@linaro.org) * squashed previous patch 1/9 and 2/9 into single (regmap based) driver
RFC V3 2020-02-16 20:20:59:
This series is based on and a follow up for
https://lore.kernel.org/patchwork/cover/868157/
("[v2,0/2] Add efuse driver for Ingenic JZ4780 SoC")
Original authors were PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Mathieu Malaterre malat@debian.org
and there are additions / code improvements by H. Nikolaus Schaller hns@goldelico.com Paul Cercueil paul@crapouillou.net
This setup works, if the dm9000 driver is compiled as a module.
Therefore it is all RFC level. It is also not completely checkpatched.
H. Nikolaus Schaller (1): MIPS: DTS: CI20: make DM9000 Ethernet controller use NVMEM to find the default MAC address
PrasannaKumar Muralidharan (5): nvmem: add driver for JZ4780 efuse Bindings: nvmem: add bindings for JZ4780 efuse Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI nvmem: MAINTAINERS: add maintainer for JZ4780 efuse driver MIPS: DTS: JZ4780: define node for JZ4780 efuse
.../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++ .../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 ++++ MAINTAINERS | 5 + arch/mips/boot/dts/ingenic/ci20.dts | 3 + arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 +- drivers/nvmem/Kconfig | 10 + drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 229 ++++++++++++++++++ 8 files changed, 331 insertions(+), 1 deletion(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml create mode 100644 drivers/nvmem/jz4780-efuse.c
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and nvmem cells.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com Signed-off-by: Paul Cercueil paul@crapouillou.net --- drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 229 +++++++++++++++++++++++++++++++++++ 3 files changed, 241 insertions(+) create mode 100644 drivers/nvmem/jz4780-efuse.c
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 35efab1ba8d9..8143e6e1dd82 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -55,6 +55,16 @@ config NVMEM_IMX_OCOTP_SCU This is a driver for the SCU On-Chip OTP Controller (OCOTP) available on i.MX8 SoCs.
+config JZ4780_EFUSE + tristate "JZ4780 EFUSE Memory Support" + depends on MACH_INGENIC || COMPILE_TEST + depends on HAS_IOMEM + help + Say Y here to include support for JZ4780 efuse memory found on + all JZ4780 SoC based devices. + To compile this driver as a module, choose M here: the module + will be called nvmem_jz4780_efuse. + config NVMEM_LPC18XX_EEPROM tristate "NXP LPC18XX EEPROM Memory Support" depends on ARCH_LPC18XX || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 6b466cd1427b..65a268d17807 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o nvmem-imx-ocotp-y := imx-ocotp.o obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o +obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o +nvmem_jz4780_efuse-y := jz4780-efuse.o obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c new file mode 100644 index 000000000000..08b63de0e9cc --- /dev/null +++ b/drivers/nvmem/jz4780-efuse.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * JZ4780 EFUSE Memory Support driver + * + * Copyright (c) 2017 PrasannaKumar Muralidharan prasannatsmkumar@gmail.com + * Copyright (c) 2020 H. Nikolaus Schaller hns@goldelico.com + */ + +/* + * Currently supports JZ4780 efuse which has 8K programmable bit. + * Efuse is separated into seven segments as below: + * + * ----------------------------------------------------------------------- + * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit | + * ----------------------------------------------------------------------- + * + * The rom itself is accessed using a 9 bit address line and an 8 word wide bus + * which reads/writes based on strobes. The strobe is configured in the config + * register and is based on number of cycles of the bus clock. + * + * Driver supports read only as the writes are done in the Factory. + */ + +#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/nvmem-provider.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/timer.h> + +#define JZ_EFUCTRL (0x0) /* Control Register */ +#define JZ_EFUCFG (0x4) /* Configure Register*/ +#define JZ_EFUSTATE (0x8) /* Status Register */ +#define JZ_EFUDATA(n) (0xC + (n) * 4) + +#define EFUCTRL_ADDR_MASK 0x3FF +#define EFUCTRL_ADDR_SHIFT 21 +#define EFUCTRL_LEN_MASK 0x1F +#define EFUCTRL_LEN_SHIFT 16 +#define EFUCTRL_PG_EN BIT(15) +#define EFUCTRL_WR_EN BIT(1) +#define EFUCTRL_RD_EN BIT(0) + +#define EFUCFG_INT_EN BIT(31) +#define EFUCFG_RD_ADJ_MASK 0xF +#define EFUCFG_RD_ADJ_SHIFT 20 +#define EFUCFG_RD_STR_MASK 0xF +#define EFUCFG_RD_STR_SHIFT 16 +#define EFUCFG_WR_ADJ_MASK 0xF +#define EFUCFG_WR_ADJ_SHIFT 12 +#define EFUCFG_WR_STR_MASK 0xFFF +#define EFUCFG_WR_STR_SHIFT 0 + +#define EFUSTATE_WR_DONE BIT(1) +#define EFUSTATE_RD_DONE BIT(0) + +struct jz4780_efuse { + struct device *dev; + struct regmap *map; + struct clk *clk; + unsigned int rd_adj; + unsigned int rd_strobe; +}; + +/* We read 32 byte chunks to avoid complexity in the driver. */ +static int jz4780_efuse_read_32bytes(struct jz4780_efuse *efuse, char *buf, + unsigned int addr) +{ + unsigned int tmp; + u32 ctrl; + int ret; + const int size = 32; + + ctrl = (addr << EFUCTRL_ADDR_SHIFT) + | ((size - 1) << EFUCTRL_LEN_SHIFT) + | EFUCTRL_RD_EN; + + regmap_update_bits(efuse->map, JZ_EFUCTRL, + (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) | + (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) | + EFUCTRL_PG_EN | EFUCTRL_WR_EN | EFUCTRL_RD_EN, ctrl); + + ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE, + tmp, tmp & EFUSTATE_RD_DONE, + 1 * MSEC_PER_SEC, 50 * MSEC_PER_SEC); + if (ret < 0) { + dev_err(efuse->dev, "Time out while reading efuse data"); + return ret; + } + + return regmap_bulk_read(efuse->map, JZ_EFUDATA(0), + buf, size / sizeof(u32)); +} + +/* main entry point */ +static int jz4780_efuse_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct jz4780_efuse *efuse = context; + int ret; + const int size = 32; + + while (bytes > 0) { + unsigned int start = offset & ~(size - 1); + unsigned int chunk = min(bytes, (start + size) - offset); + + if (start == offset && chunk == size) { + ret = jz4780_efuse_read_32bytes(efuse, val, start); + if (ret < 0) + return ret; + + } else { + char buf[32]; + + ret = jz4780_efuse_read_32bytes(efuse, buf, start); + if (ret < 0) + return ret; + + memcpy(val, &buf[offset - start], chunk); + } + + val += chunk; + offset += chunk; + bytes -= chunk; + } + + return 0; +} + +static struct nvmem_config jz4780_efuse_nvmem_config __initdata = { + .name = "jz4780-efuse", + .size = 1024, + .word_size = 1, + .stride = 1, + .owner = THIS_MODULE, + .reg_read = jz4780_efuse_read, +}; + +static const struct regmap_config jz4780_efuse_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = JZ_EFUDATA(7), +}; + +static int jz4780_efuse_probe(struct platform_device *pdev) +{ + struct nvmem_device *nvmem; + struct jz4780_efuse *efuse; + struct nvmem_config cfg; + unsigned long clk_rate; + struct device *dev = &pdev->dev; + void __iomem *regs; + + efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); + if (!efuse) + return -ENOMEM; + + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + efuse->map = devm_regmap_init_mmio(dev, regs, + &jz4780_efuse_regmap_config); + if (IS_ERR(efuse->map)) + return PTR_ERR(efuse->map); + + efuse->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(efuse->clk)) + return PTR_ERR(efuse->clk); + + clk_rate = clk_get_rate(efuse->clk); + + efuse->dev = dev; + /* + * rd_adj and rd_strobe are 4 bit values + * bus clk period * (rd_adj + 1) > 6.5ns + * bus clk period * (rd_adj + 5 + rd_strobe) > 35ns + */ + efuse->rd_adj = (((6500 * (clk_rate / 1000000)) / 1000000) + 1) - 1; + efuse->rd_strobe = ((((35000 * (clk_rate / 1000000)) / 1000000) + 1) + - 5 - efuse->rd_adj); + + if (efuse->rd_adj > 0x1F || efuse->rd_strobe > 0x1F) { + dev_err(&pdev->dev, "Cannot set clock configuration\n"); + return -EINVAL; + } + + regmap_update_bits(efuse->map, JZ_EFUCFG, + (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) | + (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT), + (efuse->rd_adj << EFUCFG_RD_ADJ_SHIFT) | + (efuse->rd_strobe << EFUCFG_RD_STR_SHIFT)); + + cfg = jz4780_efuse_nvmem_config; + cfg.dev = &pdev->dev; + cfg.priv = efuse; + + nvmem = devm_nvmem_register(dev, &cfg); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); + + platform_set_drvdata(pdev, nvmem); + + return 0; +} + +static const struct of_device_id jz4780_efuse_match[] = { + { .compatible = "ingenic,jz4780-efuse" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, jz4780_efuse_match); + +static struct platform_driver jz4780_efuse_driver = { + .probe = jz4780_efuse_probe, + .driver = { + .name = "jz4780-efuse", + .of_match_table = jz4780_efuse_match, + }, +}; +module_platform_driver(jz4780_efuse_driver); + +MODULE_AUTHOR("PrasannaKumar Muralidharan prasannatsmkumar@gmail.com"); +MODULE_AUTHOR("H. Nikolaus Schaller hns@goldelico.com"); +MODULE_AUTHOR("Paul Cercueil paul@crapouillou.net"); +MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver"); +MODULE_LICENSE("GPL v2");
Hi Nikolaus,
Le sam., févr. 22, 2020 at 11:25, H. Nikolaus Schaller hns@goldelico.com a écrit :
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and nvmem cells.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com Signed-off-by: Paul Cercueil paul@crapouillou.net
drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 229 +++++++++++++++++++++++++++++++++++ 3 files changed, 241 insertions(+) create mode 100644 drivers/nvmem/jz4780-efuse.c
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 35efab1ba8d9..8143e6e1dd82 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -55,6 +55,16 @@ config NVMEM_IMX_OCOTP_SCU This is a driver for the SCU On-Chip OTP Controller (OCOTP) available on i.MX8 SoCs.
+config JZ4780_EFUSE
- tristate "JZ4780 EFUSE Memory Support"
- depends on MACH_INGENIC || COMPILE_TEST
- depends on HAS_IOMEM
You're using regmap, so you need to select REGMAP_MMIO here.
- help
Say Y here to include support for JZ4780 efuse memory found onall JZ4780 SoC based devices.To compile this driver as a module, choose M here: the modulewill be called nvmem_jz4780_efuse.config NVMEM_LPC18XX_EEPROM tristate "NXP LPC18XX EEPROM Memory Support" depends on ARCH_LPC18XX || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 6b466cd1427b..65a268d17807 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o nvmem-imx-ocotp-y := imx-ocotp.o obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o +obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o +nvmem_jz4780_efuse-y := jz4780-efuse.o obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c new file mode 100644 index 000000000000..08b63de0e9cc --- /dev/null +++ b/drivers/nvmem/jz4780-efuse.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- JZ4780 EFUSE Memory Support driver
- Copyright (c) 2017 PrasannaKumar Muralidharan
- Copyright (c) 2020 H. Nikolaus Schaller hns@goldelico.com
- */
+/*
- Currently supports JZ4780 efuse which has 8K programmable bit.
- Efuse is separated into seven segments as below:
- | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048
bit |
- The rom itself is accessed using a 9 bit address line and an 8
word wide bus
- which reads/writes based on strobes. The strobe is configured in
the config
- register and is based on number of cycles of the bus clock.
- Driver supports read only as the writes are done in the Factory.
- */
+#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/nvmem-provider.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/timer.h>
+#define JZ_EFUCTRL (0x0) /* Control Register */ +#define JZ_EFUCFG (0x4) /* Configure Register*/ +#define JZ_EFUSTATE (0x8) /* Status Register */ +#define JZ_EFUDATA(n) (0xC + (n) * 4)
+#define EFUCTRL_ADDR_MASK 0x3FF +#define EFUCTRL_ADDR_SHIFT 21 +#define EFUCTRL_LEN_MASK 0x1F +#define EFUCTRL_LEN_SHIFT 16 +#define EFUCTRL_PG_EN BIT(15) +#define EFUCTRL_WR_EN BIT(1) +#define EFUCTRL_RD_EN BIT(0)
+#define EFUCFG_INT_EN BIT(31) +#define EFUCFG_RD_ADJ_MASK 0xF +#define EFUCFG_RD_ADJ_SHIFT 20 +#define EFUCFG_RD_STR_MASK 0xF +#define EFUCFG_RD_STR_SHIFT 16 +#define EFUCFG_WR_ADJ_MASK 0xF +#define EFUCFG_WR_ADJ_SHIFT 12 +#define EFUCFG_WR_STR_MASK 0xFFF +#define EFUCFG_WR_STR_SHIFT 0
+#define EFUSTATE_WR_DONE BIT(1) +#define EFUSTATE_RD_DONE BIT(0)
+struct jz4780_efuse {
- struct device *dev;
- struct regmap *map;
- struct clk *clk;
- unsigned int rd_adj;
- unsigned int rd_strobe;
+};
+/* We read 32 byte chunks to avoid complexity in the driver. */
I don't see how reading 32 byte chunks avoids complexity in the driver; the 'size' variable here could very well be an argument.
+static int jz4780_efuse_read_32bytes(struct jz4780_efuse *efuse, char *buf,
unsigned int addr)+{
- unsigned int tmp;
- u32 ctrl;
- int ret;
- const int size = 32;
- ctrl = (addr << EFUCTRL_ADDR_SHIFT)
| ((size - 1) << EFUCTRL_LEN_SHIFT)| EFUCTRL_RD_EN;- regmap_update_bits(efuse->map, JZ_EFUCTRL,
(EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |(EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |EFUCTRL_PG_EN | EFUCTRL_WR_EN | EFUCTRL_RD_EN, ctrl);- ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
tmp, tmp & EFUSTATE_RD_DONE,1 * MSEC_PER_SEC, 50 * MSEC_PER_SEC);- if (ret < 0) {
dev_err(efuse->dev, "Time out while reading efuse data");return ret;- }
- return regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
buf, size / sizeof(u32));+}
+/* main entry point */ +static int jz4780_efuse_read(void *context, unsigned int offset,
void *val, size_t bytes)+{
- struct jz4780_efuse *efuse = context;
- int ret;
- const int size = 32;
- while (bytes > 0) {
unsigned int start = offset & ~(size - 1);unsigned int chunk = min(bytes, (start + size) - offset);
Why do you need to check for the address alignment?
if (start == offset && chunk == size) {ret = jz4780_efuse_read_32bytes(efuse, val, start);if (ret < 0)return ret;} else {char buf[32];ret = jz4780_efuse_read_32bytes(efuse, buf, start);if (ret < 0)return ret;memcpy(val, &buf[offset - start], chunk);
Why do you need this cumbersome process of reading 32 bytes if you need less than that? This looks over-complex to me.
}val += chunk;offset += chunk;bytes -= chunk;- }
- return 0;
+}
+static struct nvmem_config jz4780_efuse_nvmem_config __initdata = {
- .name = "jz4780-efuse",
- .size = 1024,
The efuse is 8 KiB.
- .word_size = 1,
- .stride = 1,
- .owner = THIS_MODULE,
- .reg_read = jz4780_efuse_read,
+};
+static const struct regmap_config jz4780_efuse_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
- .max_register = JZ_EFUDATA(7),
+};
+static int jz4780_efuse_probe(struct platform_device *pdev) +{
- struct nvmem_device *nvmem;
- struct jz4780_efuse *efuse;
- struct nvmem_config cfg;
- unsigned long clk_rate;
- struct device *dev = &pdev->dev;
- void __iomem *regs;
- efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
- if (!efuse)
return -ENOMEM;- regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(regs))
return PTR_ERR(regs);- efuse->map = devm_regmap_init_mmio(dev, regs,
&jz4780_efuse_regmap_config);- if (IS_ERR(efuse->map))
return PTR_ERR(efuse->map);- efuse->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(efuse->clk))
return PTR_ERR(efuse->clk);- clk_rate = clk_get_rate(efuse->clk);
You didn't enable the clock before, so clk_get_rate can return a bogus value.
- efuse->dev = dev;
- /*
* rd_adj and rd_strobe are 4 bit values* bus clk period * (rd_adj + 1) > 6.5ns* bus clk period * (rd_adj + 5 + rd_strobe) > 35ns*/- efuse->rd_adj = (((6500 * (clk_rate / 1000000)) / 1000000) + 1) - 1;
I can't get my head around this calculus. Try this:
/* 1 / 6.5ns == 153846154 Hz */ efuse->rd_adj = clk_rate / 153846154;
The efuse read should be *at least* 6.5ns, so no need to bother with the -1/+1.
- efuse->rd_strobe = ((((35000 * (clk_rate / 1000000)) / 1000000) + 1)
- 5 - efuse->rd_adj);
/* 1 / 35ns == 28571429 Hz */ efuse->rd_strobe = max(0, clk_rate / 28571429 + 1 - 5 - efuse->rd_adj);
- if (efuse->rd_adj > 0x1F || efuse->rd_strobe > 0x1F) {
dev_err(&pdev->dev, "Cannot set clock configuration\n");return -EINVAL;- }
- regmap_update_bits(efuse->map, JZ_EFUCFG,
(EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |(EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),(efuse->rd_adj << EFUCFG_RD_ADJ_SHIFT) |(efuse->rd_strobe << EFUCFG_RD_STR_SHIFT));- cfg = jz4780_efuse_nvmem_config;
- cfg.dev = &pdev->dev;
- cfg.priv = efuse;
- nvmem = devm_nvmem_register(dev, &cfg);
- if (IS_ERR(nvmem))
return PTR_ERR(nvmem);- platform_set_drvdata(pdev, nvmem);
This isn't used anywhere.
- return 0;
+}
+static const struct of_device_id jz4780_efuse_match[] = {
- { .compatible = "ingenic,jz4780-efuse" },
- { /* sentinel */ },
+}; +MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
+static struct platform_driver jz4780_efuse_driver = {
- .probe = jz4780_efuse_probe,
- .driver = {
.name = "jz4780-efuse",.of_match_table = jz4780_efuse_match,- },
+}; +module_platform_driver(jz4780_efuse_driver);
+MODULE_AUTHOR("PrasannaKumar Muralidharan prasannatsmkumar@gmail.com"); +MODULE_AUTHOR("H. Nikolaus Schaller hns@goldelico.com"); +MODULE_AUTHOR("Paul Cercueil paul@crapouillou.net"); +MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
+MODULE_LICENSE("GPL v2");
2.23.0
Hi Paul,
Am 22.02.2020 um 16:38 schrieb Paul Cercueil paul@crapouillou.net:
Hi Nikolaus,
Le sam., févr. 22, 2020 at 11:25, H. Nikolaus Schaller hns@goldelico.com a écrit :
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and nvmem cells. Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com Signed-off-by: Paul Cercueil paul@crapouillou.net
drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 229 +++++++++++++++++++++++++++++++++++ 3 files changed, 241 insertions(+) create mode 100644 drivers/nvmem/jz4780-efuse.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 35efab1ba8d9..8143e6e1dd82 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -55,6 +55,16 @@ config NVMEM_IMX_OCOTP_SCU This is a driver for the SCU On-Chip OTP Controller (OCOTP) available on i.MX8 SoCs. +config JZ4780_EFUSE
- tristate "JZ4780 EFUSE Memory Support"
- depends on MACH_INGENIC || COMPILE_TEST
- depends on HAS_IOMEM
You're using regmap, so you need to select REGMAP_MMIO here.
Ok.
- help
Say Y here to include support for JZ4780 efuse memory found onall JZ4780 SoC based devices.To compile this driver as a module, choose M here: the modulewill be called nvmem_jz4780_efuse.config NVMEM_LPC18XX_EEPROM tristate "NXP LPC18XX EEPROM Memory Support" depends on ARCH_LPC18XX || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 6b466cd1427b..65a268d17807 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o nvmem-imx-ocotp-y := imx-ocotp.o obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o +obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o +nvmem_jz4780_efuse-y := jz4780-efuse.o obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c new file mode 100644 index 000000000000..08b63de0e9cc --- /dev/null +++ b/drivers/nvmem/jz4780-efuse.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- JZ4780 EFUSE Memory Support driver
- Copyright (c) 2017 PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
- Copyright (c) 2020 H. Nikolaus Schaller hns@goldelico.com
- */
+/*
- Currently supports JZ4780 efuse which has 8K programmable bit.
- Efuse is separated into seven segments as below:
- | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit |
- The rom itself is accessed using a 9 bit address line and an 8 word wide bus
- which reads/writes based on strobes. The strobe is configured in the config
- register and is based on number of cycles of the bus clock.
- Driver supports read only as the writes are done in the Factory.
- */
+#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/nvmem-provider.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/timer.h>
+#define JZ_EFUCTRL (0x0) /* Control Register */ +#define JZ_EFUCFG (0x4) /* Configure Register*/ +#define JZ_EFUSTATE (0x8) /* Status Register */ +#define JZ_EFUDATA(n) (0xC + (n) * 4)
+#define EFUCTRL_ADDR_MASK 0x3FF +#define EFUCTRL_ADDR_SHIFT 21 +#define EFUCTRL_LEN_MASK 0x1F +#define EFUCTRL_LEN_SHIFT 16 +#define EFUCTRL_PG_EN BIT(15) +#define EFUCTRL_WR_EN BIT(1) +#define EFUCTRL_RD_EN BIT(0)
+#define EFUCFG_INT_EN BIT(31) +#define EFUCFG_RD_ADJ_MASK 0xF +#define EFUCFG_RD_ADJ_SHIFT 20 +#define EFUCFG_RD_STR_MASK 0xF +#define EFUCFG_RD_STR_SHIFT 16 +#define EFUCFG_WR_ADJ_MASK 0xF +#define EFUCFG_WR_ADJ_SHIFT 12 +#define EFUCFG_WR_STR_MASK 0xFFF +#define EFUCFG_WR_STR_SHIFT 0
+#define EFUSTATE_WR_DONE BIT(1) +#define EFUSTATE_RD_DONE BIT(0)
+struct jz4780_efuse {
- struct device *dev;
- struct regmap *map;
- struct clk *clk;
- unsigned int rd_adj;
- unsigned int rd_strobe;
+};
+/* We read 32 byte chunks to avoid complexity in the driver. */
I don't see how reading 32 byte chunks avoids complexity in the driver; the 'size' variable here could very well be an argument.
I mixed your, mine and the original code.
One issue with a size argument is that regmap reads in 32bit words.
But reading the ethernet MAC address requires to fetch 6 bytes. AFAIK regmap can only read in multiples of the word size.
It must also be possible to read starting at any byte address.
+static int jz4780_efuse_read_32bytes(struct jz4780_efuse *efuse, char *buf,
unsigned int addr)+{
- unsigned int tmp;
- u32 ctrl;
- int ret;
- const int size = 32;
- ctrl = (addr << EFUCTRL_ADDR_SHIFT)
| ((size - 1) << EFUCTRL_LEN_SHIFT)| EFUCTRL_RD_EN;- regmap_update_bits(efuse->map, JZ_EFUCTRL,
(EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |(EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |EFUCTRL_PG_EN | EFUCTRL_WR_EN | EFUCTRL_RD_EN, ctrl);- ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
tmp, tmp & EFUSTATE_RD_DONE,1 * MSEC_PER_SEC, 50 * MSEC_PER_SEC);- if (ret < 0) {
dev_err(efuse->dev, "Time out while reading efuse data");return ret;- }
- return regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
buf, size / sizeof(u32));+}
+/* main entry point */ +static int jz4780_efuse_read(void *context, unsigned int offset,
void *val, size_t bytes)+{
- struct jz4780_efuse *efuse = context;
- int ret;
- const int size = 32;
- while (bytes > 0) {
unsigned int start = offset & ~(size - 1);unsigned int chunk = min(bytes, (start + size) - offset);Why do you need to check for the address alignment?
This is to decide if jz4780_efuse_read_32bytes() can directly read to the destination buffer or if we need a temporary buffer. This avoids to always use a temporary buffer.
if (start == offset && chunk == size) {ret = jz4780_efuse_read_32bytes(efuse, val, start);if (ret < 0)return ret;} else {char buf[32];ret = jz4780_efuse_read_32bytes(efuse, buf, start);if (ret < 0)return ret;memcpy(val, &buf[offset - start], chunk);Why do you need this cumbersome process of reading 32 bytes if you need less than that? This looks over-complex to me.
MAC address must allow to read 6 Bytes. I am not sure if regmap can do that.
According to the Programming Manual there are 8 registers with 32 bits each so it is probably wise to read all these 32 bytes in one big read into the regmap. So that it is never attempted to read smaller or not 32bit aligned registers. This also makes sure that bank address switching is not done for every byte.
}val += chunk;offset += chunk;bytes -= chunk;- }
- return 0;
+}
+static struct nvmem_config jz4780_efuse_nvmem_config __initdata = {
- .name = "jz4780-efuse",
- .size = 1024,
The efuse is 8 KiB.
I read the Programming Manual as 8 kBit = 1024 Byte. See for example Note 1. and 2. in section "26.2.4 EFUSE Data Register (EFUDATAn)"
- .word_size = 1,
- .stride = 1,
- .owner = THIS_MODULE,
- .reg_read = jz4780_efuse_read,
+};
+static const struct regmap_config jz4780_efuse_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
- .max_register = JZ_EFUDATA(7),
+};
+static int jz4780_efuse_probe(struct platform_device *pdev) +{
- struct nvmem_device *nvmem;
- struct jz4780_efuse *efuse;
- struct nvmem_config cfg;
- unsigned long clk_rate;
- struct device *dev = &pdev->dev;
- void __iomem *regs;
- efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
- if (!efuse)
return -ENOMEM;- regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(regs))
return PTR_ERR(regs);- efuse->map = devm_regmap_init_mmio(dev, regs,
&jz4780_efuse_regmap_config);- if (IS_ERR(efuse->map))
return PTR_ERR(efuse->map);- efuse->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(efuse->clk))
return PTR_ERR(efuse->clk);- clk_rate = clk_get_rate(efuse->clk);
You didn't enable the clock before, so clk_get_rate can return a bogus value.
Well, I copied that from your proposal for jz4780_efuse_probe(). So I don't know if that is correct or not...
How should it be solved? clk_enable() before and clk_disable() after? Or is it enabled somewhere else so that we break something if we explicitly disable?
- efuse->dev = dev;
- /*
* rd_adj and rd_strobe are 4 bit values* bus clk period * (rd_adj + 1) > 6.5ns* bus clk period * (rd_adj + 5 + rd_strobe) > 35ns*/- efuse->rd_adj = (((6500 * (clk_rate / 1000000)) / 1000000) + 1) - 1;
I can't get my head around this calculus. Try this:
I would read it as: multiply clk_rate (in MHz units) by 6.5 and divide by another 1000.
So if clock rate is e.g. 500 Mhz we calculate 6.5 * 500 / 1000 => 3(.25). 500 Mhz is equivalent to 2 ns so 2 ns * 3.25 = 6.5 ns.
But that said: there seems to be something wrong with rounding. To fulfill the
6.5 ns condition the 3.25 should be rounded up to 4.
But since the condition is defined for rd_adj + 1 it is ok to set rd_adj to 3 in this case.
/* 1 / 6.5ns == 153846154 Hz */ efuse->rd_adj = clk_rate / 153846154;
The efuse read should be *at least* 6.5ns, so no need to bother with the -1/+1.
Well, the (X + 1) - 1 looks very redundant.
So what about:
#define RD_ADJ_FACTOR (unsigned long)(10 * NSEC_PER_SEC / 65) /* 1 / 6.5ns == 153846154 Hz */
efuse->rd_adj = clk_rate / RD_ADJ_FACTOR;
- efuse->rd_strobe = ((((35000 * (clk_rate / 1000000)) / 1000000) + 1)
- 5 - efuse->rd_adj);/* 1 / 35ns == 28571429 Hz */ efuse->rd_strobe = max(0, clk_rate / 28571429 + 1 - 5 - efuse->rd_adj);
I think the original author just wanted to make the magic values a little more transparent. 35000 / 1000000 is easier to recognise as 35 ns in the programming manual than 28571429.
- if (efuse->rd_adj > 0x1F || efuse->rd_strobe > 0x1F) {
dev_err(&pdev->dev, "Cannot set clock configuration\n");return -EINVAL;- }
- regmap_update_bits(efuse->map, JZ_EFUCFG,
(EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |(EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),(efuse->rd_adj << EFUCFG_RD_ADJ_SHIFT) |(efuse->rd_strobe << EFUCFG_RD_STR_SHIFT));- cfg = jz4780_efuse_nvmem_config;
- cfg.dev = &pdev->dev;
- cfg.priv = efuse;
- nvmem = devm_nvmem_register(dev, &cfg);
- if (IS_ERR(nvmem))
return PTR_ERR(nvmem);- platform_set_drvdata(pdev, nvmem);
This isn't used anywhere.
Also copied from your proposal... But it is indeed not used anywhere.
A big question is why we need to store rd_adj and rd_strobe in the struct jz4780_efuse? They are local variables inside jz4780_efuse_probe().
So the only values used are efuse->map
- return 0;
+}
+static const struct of_device_id jz4780_efuse_match[] = {
- { .compatible = "ingenic,jz4780-efuse" },
- { /* sentinel */ },
+}; +MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
+static struct platform_driver jz4780_efuse_driver = {
- .probe = jz4780_efuse_probe,
- .driver = {
.name = "jz4780-efuse",.of_match_table = jz4780_efuse_match,- },
+}; +module_platform_driver(jz4780_efuse_driver);
+MODULE_AUTHOR("PrasannaKumar Muralidharan prasannatsmkumar@gmail.com"); +MODULE_AUTHOR("H. Nikolaus Schaller hns@goldelico.com"); +MODULE_AUTHOR("Paul Cercueil paul@crapouillou.net"); +MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
+MODULE_LICENSE("GPL v2");
2.23.0
BR and thanks, Nikolaus
Hi Nikolaus,
Le sam., févr. 22, 2020 at 18:16, H. Nikolaus Schaller hns@goldelico.com a écrit :
Hi Paul,
Am 22.02.2020 um 16:38 schrieb Paul Cercueil paul@crapouillou.net:
Hi Nikolaus,
Le sam., févr. 22, 2020 at 11:25, H. Nikolaus Schaller hns@goldelico.com a écrit :
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and nvmem cells. Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com Signed-off-by: Paul Cercueil paul@crapouillou.net
drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 229 +++++++++++++++++++++++++++++++++++ 3 files changed, 241 insertions(+) create mode 100644 drivers/nvmem/jz4780-efuse.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 35efab1ba8d9..8143e6e1dd82 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -55,6 +55,16 @@ config NVMEM_IMX_OCOTP_SCU This is a driver for the SCU On-Chip OTP Controller (OCOTP) available on i.MX8 SoCs. +config JZ4780_EFUSE
- tristate "JZ4780 EFUSE Memory Support"
- depends on MACH_INGENIC || COMPILE_TEST
- depends on HAS_IOMEM
You're using regmap, so you need to select REGMAP_MMIO here.
Ok.
I think you need to depend on OF too, since the driver only probes on devicetree.
- help
Say Y here to include support for JZ4780 efuse memory found onall JZ4780 SoC based devices.To compile this driver as a module, choose M here: the modulewill be called nvmem_jz4780_efuse.config NVMEM_LPC18XX_EEPROM tristate "NXP LPC18XX EEPROM Memory Support" depends on ARCH_LPC18XX || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 6b466cd1427b..65a268d17807 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o nvmem-imx-ocotp-y := imx-ocotp.o obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o +obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o +nvmem_jz4780_efuse-y := jz4780-efuse.o obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c new file mode 100644 index 000000000000..08b63de0e9cc --- /dev/null +++ b/drivers/nvmem/jz4780-efuse.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- JZ4780 EFUSE Memory Support driver
- Copyright (c) 2017 PrasannaKumar Muralidharan
- Copyright (c) 2020 H. Nikolaus Schaller hns@goldelico.com
- */
+/*
- Currently supports JZ4780 efuse which has 8K programmable bit.
- Efuse is separated into seven segments as below:
- | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit |
2048 bit |
- The rom itself is accessed using a 9 bit address line and an 8
word wide bus
- which reads/writes based on strobes. The strobe is configured
in the config
- register and is based on number of cycles of the bus clock.
- Driver supports read only as the writes are done in the
Factory.
- */
+#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/nvmem-provider.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/timer.h>
+#define JZ_EFUCTRL (0x0) /* Control Register */ +#define JZ_EFUCFG (0x4) /* Configure Register*/ +#define JZ_EFUSTATE (0x8) /* Status Register */ +#define JZ_EFUDATA(n) (0xC + (n) * 4)
+#define EFUCTRL_ADDR_MASK 0x3FF +#define EFUCTRL_ADDR_SHIFT 21 +#define EFUCTRL_LEN_MASK 0x1F +#define EFUCTRL_LEN_SHIFT 16 +#define EFUCTRL_PG_EN BIT(15) +#define EFUCTRL_WR_EN BIT(1) +#define EFUCTRL_RD_EN BIT(0)
+#define EFUCFG_INT_EN BIT(31) +#define EFUCFG_RD_ADJ_MASK 0xF +#define EFUCFG_RD_ADJ_SHIFT 20 +#define EFUCFG_RD_STR_MASK 0xF +#define EFUCFG_RD_STR_SHIFT 16 +#define EFUCFG_WR_ADJ_MASK 0xF +#define EFUCFG_WR_ADJ_SHIFT 12 +#define EFUCFG_WR_STR_MASK 0xFFF +#define EFUCFG_WR_STR_SHIFT 0
+#define EFUSTATE_WR_DONE BIT(1) +#define EFUSTATE_RD_DONE BIT(0)
+struct jz4780_efuse {
- struct device *dev;
- struct regmap *map;
- struct clk *clk;
- unsigned int rd_adj;
- unsigned int rd_strobe;
+};
+/* We read 32 byte chunks to avoid complexity in the driver. */
I don't see how reading 32 byte chunks avoids complexity in the driver; the 'size' variable here could very well be an argument.
I mixed your, mine and the original code.
One issue with a size argument is that regmap reads in 32bit words.
But reading the ethernet MAC address requires to fetch 6 bytes. AFAIK regmap can only read in multiples of the word size.
It must also be possible to read starting at any byte address.
Right, I didn't think about byte access.
+static int jz4780_efuse_read_32bytes(struct jz4780_efuse *efuse, char *buf,
unsigned int addr)+{
- unsigned int tmp;
- u32 ctrl;
- int ret;
- const int size = 32;
- ctrl = (addr << EFUCTRL_ADDR_SHIFT)
| ((size - 1) << EFUCTRL_LEN_SHIFT)| EFUCTRL_RD_EN;- regmap_update_bits(efuse->map, JZ_EFUCTRL,
(EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |(EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |EFUCTRL_PG_EN | EFUCTRL_WR_EN | EFUCTRL_RD_EN, ctrl);- ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
tmp, tmp & EFUSTATE_RD_DONE,1 * MSEC_PER_SEC, 50 * MSEC_PER_SEC);- if (ret < 0) {
dev_err(efuse->dev, "Time out while reading efuse data");return ret;- }
- return regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
buf, size / sizeof(u32));+}
+/* main entry point */ +static int jz4780_efuse_read(void *context, unsigned int offset,
void *val, size_t bytes)+{
- struct jz4780_efuse *efuse = context;
- int ret;
- const int size = 32;
- while (bytes > 0) {
unsigned int start = offset & ~(size - 1);unsigned int chunk = min(bytes, (start + size) - offset);Why do you need to check for the address alignment?
This is to decide if jz4780_efuse_read_32bytes() can directly read to the destination buffer or if we need a temporary buffer. This avoids to always use a temporary buffer.
Just always use a temporary buffer. It's not like this will be called very often anyway. That makes the code simpler.
if (start == offset && chunk == size) {ret = jz4780_efuse_read_32bytes(efuse, val, start);if (ret < 0)return ret;} else {char buf[32];ret = jz4780_efuse_read_32bytes(efuse, buf, start);if (ret < 0)return ret;memcpy(val, &buf[offset - start], chunk);Why do you need this cumbersome process of reading 32 bytes if you need less than that? This looks over-complex to me.
MAC address must allow to read 6 Bytes. I am not sure if regmap can do that.
According to the Programming Manual there are 8 registers with 32 bits each so it is probably wise to read all these 32 bytes in one big read into the regmap. So that it is never attempted to read smaller or not 32bit aligned registers. This also makes sure that bank address switching is not done for every byte.
Honestly, it doesn't have to be fast. You could very well read byte per byte. Then you wouldn't have to care about non-aligned addresses or sizes, and the driver would be much simpler.
}val += chunk;offset += chunk;bytes -= chunk;- }
- return 0;
+}
+static struct nvmem_config jz4780_efuse_nvmem_config __initdata = {
- .name = "jz4780-efuse",
- .size = 1024,
The efuse is 8 KiB.
I read the Programming Manual as 8 kBit = 1024 Byte. See for example Note 1. and 2. in section "26.2.4 EFUSE Data Register (EFUDATAn)"
Right. 8 Kib, not KiB.
- .word_size = 1,
- .stride = 1,
- .owner = THIS_MODULE,
- .reg_read = jz4780_efuse_read,
+};
+static const struct regmap_config jz4780_efuse_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
- .max_register = JZ_EFUDATA(7),
+};
+static int jz4780_efuse_probe(struct platform_device *pdev) +{
- struct nvmem_device *nvmem;
- struct jz4780_efuse *efuse;
- struct nvmem_config cfg;
- unsigned long clk_rate;
- struct device *dev = &pdev->dev;
- void __iomem *regs;
- efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
- if (!efuse)
return -ENOMEM;- regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(regs))
return PTR_ERR(regs);- efuse->map = devm_regmap_init_mmio(dev, regs,
&jz4780_efuse_regmap_config);- if (IS_ERR(efuse->map))
return PTR_ERR(efuse->map);- efuse->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(efuse->clk))
return PTR_ERR(efuse->clk);- clk_rate = clk_get_rate(efuse->clk);
You didn't enable the clock before, so clk_get_rate can return a bogus value.
Well, I copied that from your proposal for jz4780_efuse_probe(). So I don't know if that is correct or not... How should it be solved? clk_enable() before and clk_disable() after? Or is it enabled somewhere else so that we break something if we explicitly disable?
clk_prepare_enable() here, and clk_disable_unprepare() in the remove callback or in a function passed to devm_add_action_or_reset().
- efuse->dev = dev;
- /*
* rd_adj and rd_strobe are 4 bit values* bus clk period * (rd_adj + 1) > 6.5ns* bus clk period * (rd_adj + 5 + rd_strobe) > 35ns*/- efuse->rd_adj = (((6500 * (clk_rate / 1000000)) / 1000000) + 1)
- 1;
I can't get my head around this calculus. Try this:
I would read it as: multiply clk_rate (in MHz units) by 6.5 and divide by another 1000.
So if clock rate is e.g. 500 Mhz we calculate 6.5 * 500 / 1000 => 3(.25). 500 Mhz is equivalent to 2 ns so 2 ns * 3.25 = 6.5 ns.
Yes, I'm not saying that the calculus is wrong. But it multiplies picoseconds with MHz, then divides by 1000000, so it's not easy to understand.
But that said: there seems to be something wrong with rounding. To fulfill the
6.5 ns condition the 3.25 should be rounded up to 4.
But since the condition is defined for rd_adj + 1 it is ok to set rd_adj to 3 in this case.
/* 1 / 6.5ns == 153846154 Hz */ efuse->rd_adj = clk_rate / 153846154;
The efuse read should be *at least* 6.5ns, so no need to bother with the -1/+1.
Well, the (X + 1) - 1 looks very redundant.
So what about:
#define RD_ADJ_FACTOR (unsigned long)(10 * NSEC_PER_SEC / 65) /* 1 / 6.5ns == 153846154 Hz */
efuse->rd_adj = clk_rate / RD_ADJ_FACTOR;
Well, you still need the comment after the #define, so why use a #define in the first place?
- efuse->rd_strobe = ((((35000 * (clk_rate / 1000000)) / 1000000)
- 5 - efuse->rd_adj);/* 1 / 35ns == 28571429 Hz */ efuse->rd_strobe = max(0, clk_rate / 28571429 + 1 - 5 - efuse->rd_adj);
I think the original author just wanted to make the magic values a little more transparent. 35000 / 1000000 is easier to recognise as 35 ns in the programming manual than 28571429.
35000 / 1000000 is 35ms, not 35ns.
28571429 Hz is easy to recognize as 35ns when there's a comment right above saying where that value comes from.
- if (efuse->rd_adj > 0x1F || efuse->rd_strobe > 0x1F) {
dev_err(&pdev->dev, "Cannot set clock configuration\n");return -EINVAL;- }
- regmap_update_bits(efuse->map, JZ_EFUCFG,
(EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |(EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),(efuse->rd_adj << EFUCFG_RD_ADJ_SHIFT) |(efuse->rd_strobe << EFUCFG_RD_STR_SHIFT));- cfg = jz4780_efuse_nvmem_config;
- cfg.dev = &pdev->dev;
- cfg.priv = efuse;
- nvmem = devm_nvmem_register(dev, &cfg);
- if (IS_ERR(nvmem))
return PTR_ERR(nvmem);- platform_set_drvdata(pdev, nvmem);
This isn't used anywhere.
Also copied from your proposal... But it is indeed not used anywhere.
My code wasn't upstream-ready, and wasn't even tested on real hardware. I'm reviewing the driver for mainline inclusion now.
A big question is why we need to store rd_adj and rd_strobe in the struct jz4780_efuse? They are local variables inside jz4780_efuse_probe().
Maybe move the calculation of rd_adj / rd_strobe to a new function that's called from the probe, and have these local variables within this function.
So the only values used are efuse->map
- return 0;
+}
+static const struct of_device_id jz4780_efuse_match[] = {
- { .compatible = "ingenic,jz4780-efuse" },
- { /* sentinel */ },
+}; +MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
+static struct platform_driver jz4780_efuse_driver = {
- .probe = jz4780_efuse_probe,
- .driver = {
.name = "jz4780-efuse",.of_match_table = jz4780_efuse_match,- },
+}; +module_platform_driver(jz4780_efuse_driver);
+MODULE_AUTHOR("PrasannaKumar Muralidharan prasannatsmkumar@gmail.com"); +MODULE_AUTHOR("H. Nikolaus Schaller hns@goldelico.com"); +MODULE_AUTHOR("Paul Cercueil paul@crapouillou.net"); +MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
+MODULE_LICENSE("GPL v2");
2.23.0
BR and thanks, Nikolaus
Hi Paul,
Am 22.02.2020 um 19:13 schrieb Paul Cercueil paul@crapouillou.net:
Hi Nikolaus,
Le sam., févr. 22, 2020 at 18:16, H. Nikolaus Schaller hns@goldelico.com a écrit :
Hi Paul,
Am 22.02.2020 um 16:38 schrieb Paul Cercueil paul@crapouillou.net: Hi Nikolaus, Le sam., févr. 22, 2020 at 11:25, H. Nikolaus Schaller hns@goldelico.com a écrit :
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and nvmem cells. Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com Signed-off-by: Paul Cercueil paul@crapouillou.net
drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 229 +++++++++++++++++++++++++++++++++++ 3 files changed, 241 insertions(+) create mode 100644 drivers/nvmem/jz4780-efuse.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 35efab1ba8d9..8143e6e1dd82 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -55,6 +55,16 @@ config NVMEM_IMX_OCOTP_SCU This is a driver for the SCU On-Chip OTP Controller (OCOTP) available on i.MX8 SoCs. +config JZ4780_EFUSE
- tristate "JZ4780 EFUSE Memory Support"
- depends on MACH_INGENIC || COMPILE_TEST
- depends on HAS_IOMEM
You're using regmap, so you need to select REGMAP_MMIO here.
Ok.
I think you need to depend on OF too, since the driver only probes on devicetree.
Ok, added for v6.
- help
Say Y here to include support for JZ4780 efuse memory found onall JZ4780 SoC based devices.To compile this driver as a module, choose M here: the modulewill be called nvmem_jz4780_efuse.config NVMEM_LPC18XX_EEPROM tristate "NXP LPC18XX EEPROM Memory Support" depends on ARCH_LPC18XX || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 6b466cd1427b..65a268d17807 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o nvmem-imx-ocotp-y := imx-ocotp.o obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o +obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o +nvmem_jz4780_efuse-y := jz4780-efuse.o obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c new file mode 100644 index 000000000000..08b63de0e9cc --- /dev/null +++ b/drivers/nvmem/jz4780-efuse.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- JZ4780 EFUSE Memory Support driver
- Copyright (c) 2017 PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
- Copyright (c) 2020 H. Nikolaus Schaller hns@goldelico.com
- */
+/*
- Currently supports JZ4780 efuse which has 8K programmable bit.
- Efuse is separated into seven segments as below:
- | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit |
- The rom itself is accessed using a 9 bit address line and an 8 word wide bus
- which reads/writes based on strobes. The strobe is configured in the config
- register and is based on number of cycles of the bus clock.
- Driver supports read only as the writes are done in the Factory.
- */
+#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/nvmem-provider.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/timer.h>
+#define JZ_EFUCTRL (0x0) /* Control Register */ +#define JZ_EFUCFG (0x4) /* Configure Register*/ +#define JZ_EFUSTATE (0x8) /* Status Register */ +#define JZ_EFUDATA(n) (0xC + (n) * 4)
+#define EFUCTRL_ADDR_MASK 0x3FF +#define EFUCTRL_ADDR_SHIFT 21 +#define EFUCTRL_LEN_MASK 0x1F +#define EFUCTRL_LEN_SHIFT 16 +#define EFUCTRL_PG_EN BIT(15) +#define EFUCTRL_WR_EN BIT(1) +#define EFUCTRL_RD_EN BIT(0)
+#define EFUCFG_INT_EN BIT(31) +#define EFUCFG_RD_ADJ_MASK 0xF +#define EFUCFG_RD_ADJ_SHIFT 20 +#define EFUCFG_RD_STR_MASK 0xF +#define EFUCFG_RD_STR_SHIFT 16 +#define EFUCFG_WR_ADJ_MASK 0xF +#define EFUCFG_WR_ADJ_SHIFT 12 +#define EFUCFG_WR_STR_MASK 0xFFF +#define EFUCFG_WR_STR_SHIFT 0
+#define EFUSTATE_WR_DONE BIT(1) +#define EFUSTATE_RD_DONE BIT(0)
+struct jz4780_efuse {
- struct device *dev;
- struct regmap *map;
- struct clk *clk;
- unsigned int rd_adj;
- unsigned int rd_strobe;
+};
+/* We read 32 byte chunks to avoid complexity in the driver. */
I don't see how reading 32 byte chunks avoids complexity in the driver; the 'size' variable here could very well be an argument.
I mixed your, mine and the original code. One issue with a size argument is that regmap reads in 32bit words. But reading the ethernet MAC address requires to fetch 6 bytes. AFAIK regmap can only read in multiples of the word size. It must also be possible to read starting at any byte address.
Right, I didn't think about byte access.
+static int jz4780_efuse_read_32bytes(struct jz4780_efuse *efuse, char *buf,
unsigned int addr)+{
- unsigned int tmp;
- u32 ctrl;
- int ret;
- const int size = 32;
- ctrl = (addr << EFUCTRL_ADDR_SHIFT)
| ((size - 1) << EFUCTRL_LEN_SHIFT)| EFUCTRL_RD_EN;- regmap_update_bits(efuse->map, JZ_EFUCTRL,
(EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |(EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |EFUCTRL_PG_EN | EFUCTRL_WR_EN | EFUCTRL_RD_EN, ctrl);- ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
tmp, tmp & EFUSTATE_RD_DONE,1 * MSEC_PER_SEC, 50 * MSEC_PER_SEC);- if (ret < 0) {
dev_err(efuse->dev, "Time out while reading efuse data");return ret;- }
- return regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
buf, size / sizeof(u32));+}
+/* main entry point */ +static int jz4780_efuse_read(void *context, unsigned int offset,
void *val, size_t bytes)+{
- struct jz4780_efuse *efuse = context;
- int ret;
- const int size = 32;
- while (bytes > 0) {
unsigned int start = offset & ~(size - 1);unsigned int chunk = min(bytes, (start + size) - offset);Why do you need to check for the address alignment?
This is to decide if jz4780_efuse_read_32bytes() can directly read to the destination buffer or if we need a temporary buffer. This avoids to always use a temporary buffer.
Just always use a temporary buffer. It's not like this will be called very often anyway. That makes the code simpler.
Ok.
This did allow me to inline (and remove) the jz4780_efuse_read_32bytes() function and make the size = 32 a #define JZ_EFU_READ_SIZE 32
I have tested and
dd if=/sys/devices/platform/134100d0.efuse/jz4780-efuse0/nvmem bs=1 skip=34 count=6 status=none | xxd
does work and return the MAC address.
BTW: the HDMI Key and Secure Boot sectors seem to be zeroed out on my board.
if (start == offset && chunk == size) {ret = jz4780_efuse_read_32bytes(efuse, val, start);if (ret < 0)return ret;} else {char buf[32];ret = jz4780_efuse_read_32bytes(efuse, buf, start);if (ret < 0)return ret;memcpy(val, &buf[offset - start], chunk);Why do you need this cumbersome process of reading 32 bytes if you need less than that? This looks over-complex to me.
MAC address must allow to read 6 Bytes. I am not sure if regmap can do that. According to the Programming Manual there are 8 registers with 32 bits each so it is probably wise to read all these 32 bytes in one big read into the regmap. So that it is never attempted to read smaller or not 32bit aligned registers. This also makes sure that bank address switching is not done for every byte.
Honestly, it doesn't have to be fast.
Agreed.
You could very well read byte per byte. Then you wouldn't have to care about non-aligned addresses or sizes, and the driver would be much simpler.
Well, the regmap API has no byte access. So we need to read a block and extract single bytes anyways. This is what my algorithm does.
}val += chunk;offset += chunk;bytes -= chunk;- }
- return 0;
+}
+static struct nvmem_config jz4780_efuse_nvmem_config __initdata = {
- .name = "jz4780-efuse",
- .size = 1024,
The efuse is 8 KiB.
I read the Programming Manual as 8 kBit = 1024 Byte. See for example Note 1. and 2. in section "26.2.4 EFUSE Data Register (EFUDATAn)"
Right. 8 Kib, not KiB.
- .word_size = 1,
- .stride = 1,
- .owner = THIS_MODULE,
- .reg_read = jz4780_efuse_read,
+};
+static const struct regmap_config jz4780_efuse_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
- .max_register = JZ_EFUDATA(7),
+};
+static int jz4780_efuse_probe(struct platform_device *pdev) +{
- struct nvmem_device *nvmem;
- struct jz4780_efuse *efuse;
- struct nvmem_config cfg;
- unsigned long clk_rate;
- struct device *dev = &pdev->dev;
- void __iomem *regs;
- efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
- if (!efuse)
return -ENOMEM;- regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(regs))
return PTR_ERR(regs);- efuse->map = devm_regmap_init_mmio(dev, regs,
&jz4780_efuse_regmap_config);- if (IS_ERR(efuse->map))
return PTR_ERR(efuse->map);- efuse->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(efuse->clk))
return PTR_ERR(efuse->clk);- clk_rate = clk_get_rate(efuse->clk);
You didn't enable the clock before, so clk_get_rate can return a bogus value.
Well, I copied that from your proposal for jz4780_efuse_probe(). So I don't know if that is correct or not... How should it be solved? clk_enable() before and clk_disable() after? Or is it enabled somewhere else so that we break something if we explicitly disable?
clk_prepare_enable() here, and clk_disable_unprepare() in the remove callback or in a function passed to devm_add_action_or_reset().
Added to a remove callback.
- efuse->dev = dev;
- /*
* rd_adj and rd_strobe are 4 bit values* bus clk period * (rd_adj + 1) > 6.5ns
translates into
rd_adj > 6.5ns / clk_period -1 rd_adj >= 6.5ns / clk_period
* bus clk period * (rd_adj + 5 + rd_strobe) > 35ns
translates into
rd_strobe > 35 ns / clk_period - 5 - rd_adj rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
*/- efuse->rd_adj = (((6500 * (clk_rate / 1000000)) / 1000000) + 1) - 1;
I can't get my head around this calculus. Try this:
I would read it as: multiply clk_rate (in MHz units) by 6.5 and divide by another 1000. So if clock rate is e.g. 500 Mhz we calculate 6.5 * 500 / 1000 => 3(.25). 500 Mhz is equivalent to 2 ns so 2 ns * 3.25 = 6.5 ns.
Yes, I'm not saying that the calculus is wrong. But it multiplies picoseconds with MHz, then divides by 1000000, so it's not easy to understand.
Maybe this is also because there might be an overflow on 32 bit compiler if done differently.
Taking this into account I also have removed the rd_strobe = max(0, ...) mechanism since there is a check for the unsigned result being <= 15 to fit into the 4 bits. So negative values for rd_strobe lead to an error abort.
But that said: there seems to be something wrong with rounding. To fulfill the
6.5 ns condition the 3.25 should be rounded up to 4.
But since the condition is defined for rd_adj + 1 it is ok to set rd_adj to 3 in this case.
/* 1 / 6.5ns == 153846154 Hz */ efuse->rd_adj = clk_rate / 153846154; The efuse read should be *at least* 6.5ns, so no need to bother with the -1/+1.
Well, the (X + 1) - 1 looks very redundant. So what about: #define RD_ADJ_FACTOR (unsigned long)(10 * NSEC_PER_SEC / 65) /* 1 / 6.5ns == 153846154 Hz */ efuse->rd_adj = clk_rate / RD_ADJ_FACTOR;
Well, you still need the comment after the #define, so why use a #define in the first place?
Ok, agreed.
- efuse->rd_strobe = ((((35000 * (clk_rate / 1000000)) / 1000000) + 1)
- 5 - efuse->rd_adj);/* 1 / 35ns == 28571429 Hz */ efuse->rd_strobe = max(0, clk_rate / 28571429 + 1 - 5 - efuse->rd_adj);
I think the original author just wanted to make the magic values a little more transparent. 35000 / 1000000 is easier to recognise as 35 ns in the programming manual than 28571429.
35000 / 1000000 is 35ms, not 35ns.
28571429 Hz is easy to recognize as 35ns when there's a comment right above saying where that value comes from.
Ok.
- if (efuse->rd_adj > 0x1F || efuse->rd_strobe > 0x1F) {
dev_err(&pdev->dev, "Cannot set clock configuration\n");return -EINVAL;- }
- regmap_update_bits(efuse->map, JZ_EFUCFG,
(EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |(EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),(efuse->rd_adj << EFUCFG_RD_ADJ_SHIFT) |(efuse->rd_strobe << EFUCFG_RD_STR_SHIFT));- cfg = jz4780_efuse_nvmem_config;
- cfg.dev = &pdev->dev;
- cfg.priv = efuse;
- nvmem = devm_nvmem_register(dev, &cfg);
- if (IS_ERR(nvmem))
return PTR_ERR(nvmem);- platform_set_drvdata(pdev, nvmem);
This isn't used anywhere.
Also copied from your proposal... But it is indeed not used anywhere.
Now it is used for the remove function - but storing the efuse pointer and not nvmem. Maybe this was intended initially anyways.
My code wasn't upstream-ready, and wasn't even tested on real hardware. I'm reviewing the driver for mainline inclusion now.
Ah, ok. I didn't really think about you switching roles and me in between :)
A big question is why we need to store rd_adj and rd_strobe in the struct jz4780_efuse? They are local variables inside jz4780_efuse_probe().
Maybe move the calculation of rd_adj / rd_strobe to a new function that's called from the probe, and have these local variables within this function.
I do not see a need for a special calculation function. It is not reused anywhere, done only once and not very complex.
So I have made rd_adj / rd_strobe local variables inside of jz4780_efuse_probe().
So the only values used are efuse->map
- return 0;
+}
+static const struct of_device_id jz4780_efuse_match[] = {
- { .compatible = "ingenic,jz4780-efuse" },
- { /* sentinel */ },
+}; +MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
+static struct platform_driver jz4780_efuse_driver = {
- .probe = jz4780_efuse_probe,
- .driver = {
.name = "jz4780-efuse",.of_match_table = jz4780_efuse_match,- },
+}; +module_platform_driver(jz4780_efuse_driver);
+MODULE_AUTHOR("PrasannaKumar Muralidharan prasannatsmkumar@gmail.com"); +MODULE_AUTHOR("H. Nikolaus Schaller hns@goldelico.com"); +MODULE_AUTHOR("Paul Cercueil paul@crapouillou.net"); +MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
+MODULE_LICENSE("GPL v2");
2.23.0
BR and thanks, Nikolaus
[PATCH v6] will come now.
BR and thanks, Nikolaus
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com [converted to yaml] Signed-off-by: Andreas Kemnade andreas@kemnade.info --- .../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..09a8ef937750 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic JZ EFUSE driver bindings + +maintainers: + - PrasannaKumar Muralidharan prasannatsmkumar@gmail.com + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - ingenic,jz4780-efuse + + reg: + maxItems: 1 + + clocks: + # Handle for the ahb for the efuse. + maxItems: 1 + + clock-names: + items: + - const: ahb2 + +required: + - compatible + - reg + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/jz4780-cgu.h> + + efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0x2c>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "ahb2"; + }; + +...
On Sat, 22 Feb 2020 11:25:37 +0100 "H. Nikolaus Schaller" hns@goldelico.com wrote:
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com [converted to yaml] Signed-off-by: Andreas Kemnade andreas@kemnade.info
.../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..09a8ef937750 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Ingenic JZ EFUSE driver bindings
+maintainers:
- PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
+allOf:
- $ref: "nvmem.yaml#"
+properties:
- compatible:
- enum:
- ingenic,jz4780-efuse- reg:
- maxItems: 1
- clocks:
- # Handle for the ahb for the efuse.
- maxItems: 1
- clock-names:
- items:
- const: ahb2+required:
- compatible
- reg
- clock-names
- clocks ?
In my first try there was "clock" without s which caused the trouble.
Regards, Andreas
Am 22.02.2020 um 11:54 schrieb Andreas Kemnade andreas@kemnade.info:
On Sat, 22 Feb 2020 11:25:37 +0100 "H. Nikolaus Schaller" hns@goldelico.com wrote:
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com [converted to yaml] Signed-off-by: Andreas Kemnade andreas@kemnade.info
.../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..09a8ef937750 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Ingenic JZ EFUSE driver bindings
+maintainers:
- PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
+allOf:
- $ref: "nvmem.yaml#"
+properties:
- compatible:
- enum:
- ingenic,jz4780-efuse- reg:
- maxItems: 1
- clocks:
- # Handle for the ahb for the efuse.
- maxItems: 1
- clock-names:
- items:
- const: ahb2+required:
- compatible
- reg
- clock-names
- clocks ?
In my first try there was "clock" without s which caused the trouble.
Ah, ok. Seems I have mis-interpreted this.
BR and thanks, Nikolaus
On Sat, 22 Feb 2020 11:25:37 +0100 "H. Nikolaus Schaller" hns@goldelico.com wrote:
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com [converted to yaml] Signed-off-by: Andreas Kemnade andreas@kemnade.info
.../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..09a8ef937750 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Ingenic JZ EFUSE driver bindings
+maintainers:
- PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
+allOf:
- $ref: "nvmem.yaml#"
+properties:
- compatible:
- enum:
- ingenic,jz4780-efuse- reg:
- maxItems: 1
- clocks:
- # Handle for the ahb for the efuse.
- maxItems: 1
- clock-names:
- items:
- const: ahb2
as Rob said: probably not needed, since it is a single clock, and the driver uses devm_clk_get(dev, NULL), so it should be prepared for that without any extra work.
+required:
- compatible
- reg
- clock-names
so it is not required here (but "- clocks" (not "- clock") as said in earlier mail).
+unevaluatedProperties: false
+examples:
- |
- #include <dt-bindings/clock/jz4780-cgu.h>
- efuse@134100d0 {
compatible = "ingenic,jz4780-efuse";reg = <0x134100d0 0x2c>;clocks = <&cgu JZ4780_CLK_AHB2>;clock-names = "ahb2";
and not required here.
Regards, Andreas
Am 22.02.2020 um 16:57 schrieb Andreas Kemnade andreas@kemnade.info:
On Sat, 22 Feb 2020 11:25:37 +0100 "H. Nikolaus Schaller" hns@goldelico.com wrote:
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com [converted to yaml] Signed-off-by: Andreas Kemnade andreas@kemnade.info
.../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..09a8ef937750 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Ingenic JZ EFUSE driver bindings
+maintainers:
- PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
+allOf:
- $ref: "nvmem.yaml#"
+properties:
- compatible:
- enum:
- ingenic,jz4780-efuse- reg:
- maxItems: 1
- clocks:
- # Handle for the ahb for the efuse.
- maxItems: 1
- clock-names:
- items:
- const: ahb2as Rob said: probably not needed, since it is a single clock, and the driver uses devm_clk_get(dev, NULL), so it should be prepared for that without any extra work.
The question is if a specific driver implementation should determine what the DT requires or the other way round. I don't know...
I did interpret Rob's comment differently: there was
- "clock-names" Must be "bus_clk"
and he did say:
'clk' is redundant. How about 'ahb'?
So I thought he refers to the _clk suffix?
+required:
- compatible
- reg
- clock-names
so it is not required here (but "- clocks" (not "- clock") as said in earlier mail).
Well, this is another example where I do not yet see any improvement by yaml. It is the same amount of guessing what should be written where. Is this to be added or not? When is it and why, when not and why?
BR and thanks, Nikolaus
On Sat, 22 Feb 2020 17:34:06 +0100 "H. Nikolaus Schaller" hns@goldelico.com wrote:
Am 22.02.2020 um 16:57 schrieb Andreas Kemnade andreas@kemnade.info:
On Sat, 22 Feb 2020 11:25:37 +0100 "H. Nikolaus Schaller" hns@goldelico.com wrote:
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com [converted to yaml] Signed-off-by: Andreas Kemnade andreas@kemnade.info
.../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..09a8ef937750 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Ingenic JZ EFUSE driver bindings
+maintainers:
- PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
+allOf:
- $ref: "nvmem.yaml#"
+properties:
- compatible:
- enum:
- ingenic,jz4780-efuse- reg:
- maxItems: 1
- clocks:
- # Handle for the ahb for the efuse.
- maxItems: 1
- clock-names:
- items:
- const: ahb2as Rob said: probably not needed, since it is a single clock, and the driver uses devm_clk_get(dev, NULL), so it should be prepared for that without any extra work.
The question is if a specific driver implementation should determine what the DT requires or the other way round. I don't know...
I did interpret Rob's comment differently: there was
- "clock-names" Must be "bus_clk"
and he did say:
'clk' is redundant. How about 'ahb'?
So I thought he refers to the _clk suffix?
and he said to my first try: ---
- clock-names:
- items:
- const: bus_clk
My prior comment still applies.
Also, for a single clock, you don't really need a name. ---
Regards, Andreas
Am 22.02.2020 um 17:46 schrieb Andreas Kemnade andreas@kemnade.info:
On Sat, 22 Feb 2020 17:34:06 +0100 "H. Nikolaus Schaller" hns@goldelico.com wrote:
Am 22.02.2020 um 16:57 schrieb Andreas Kemnade andreas@kemnade.info:
On Sat, 22 Feb 2020 11:25:37 +0100 "H. Nikolaus Schaller" hns@goldelico.com wrote:
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com [converted to yaml] Signed-off-by: Andreas Kemnade andreas@kemnade.info
.../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..09a8ef937750 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Ingenic JZ EFUSE driver bindings
+maintainers:
- PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
+allOf:
- $ref: "nvmem.yaml#"
+properties:
- compatible:
- enum:
- ingenic,jz4780-efuse- reg:
- maxItems: 1
- clocks:
- # Handle for the ahb for the efuse.
- maxItems: 1
- clock-names:
- items:
- const: ahb2as Rob said: probably not needed, since it is a single clock, and the driver uses devm_clk_get(dev, NULL), so it should be prepared for that without any extra work.
The question is if a specific driver implementation should determine what the DT requires or the other way round. I don't know...
I did interpret Rob's comment differently: there was
- "clock-names" Must be "bus_clk"
and he did say:
'clk' is redundant. How about 'ahb'?
So I thought he refers to the _clk suffix?
and he said to my first try:
- clock-names:
- items:
- const: bus_clkMy prior comment still applies.
Also, for a single clock, you don't really need a name.
Ah, ok. I may have missed that.
BR and thanks, Nikolaus
On Sat, 22 Feb 2020 17:34:06 +0100 "H. Nikolaus Schaller" hns@goldelico.com wrote:
Am 22.02.2020 um 16:57 schrieb Andreas Kemnade andreas@kemnade.info:
On Sat, 22 Feb 2020 11:25:37 +0100 "H. Nikolaus Schaller" hns@goldelico.com wrote:
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com [converted to yaml] Signed-off-by: Andreas Kemnade andreas@kemnade.info
.../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..09a8ef937750 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Ingenic JZ EFUSE driver bindings
+maintainers:
- PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
+allOf:
- $ref: "nvmem.yaml#"
+properties:
- compatible:
- enum:
- ingenic,jz4780-efuse- reg:
- maxItems: 1
- clocks:
- # Handle for the ahb for the efuse.
- maxItems: 1
- clock-names:
- items:
- const: ahb2as Rob said: probably not needed, since it is a single clock, and the driver uses devm_clk_get(dev, NULL), so it should be prepared for that without any extra work.
The question is if a specific driver implementation should determine what the DT requires or the other way round. I don't know...
I did interpret Rob's comment differently: there was
- "clock-names" Must be "bus_clk"
and he did say:
'clk' is redundant. How about 'ahb'?
So I thought he refers to the _clk suffix?
+required:
- compatible
- reg
- clock-names
so it is not required here (but "- clocks" (not "- clock") as said in earlier mail).
Well, this is another example where I do not yet see any improvement by yaml. It is the same amount of guessing what should be written where. Is this to be added or not? When is it and why, when not and why?
well, this is the list of required properties which have to be an any devicetree using that device, the conversion of the comments for the properties in the .txt-file. So, if you do not declare a property before, you cannot specify that it is required. So if we drop the definition of clock-names we cannot declare it as required.
Regards, Andreas
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org --- .../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse
diff --git a/Documentation/ABI/testing/sysfs-driver-jz4780-efuse b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file mode 100644 index 000000000000..bb6f5d6ceea0 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse @@ -0,0 +1,16 @@ +What: /sys/devices/*/<our-device>/nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com +Description: read-only access to the efuse on the Ingenic JZ4780 SoC + The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot key +Users: any user space application which wants to read the Chip + and Customer ID
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS index a0d86490c2c6..5bab216d8fe9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8270,6 +8270,11 @@ M: Zubair Lutfullah Kakakhel Zubair.Kakakhel@imgtec.com S: Maintained F: drivers/dma/dma-jz4780.c
+INGENIC JZ4780 EFUSE Driver +M: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com +S: Maintained +F: drivers/nvmem/jz4780-efuse.c + INGENIC JZ4780 NAND DRIVER M: Harvey Hunt harveyhuntnexus@gmail.com L: linux-mtd@lists.infradead.org
From: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com
This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and the ethernet mac address for the davicom dm9000 chip on the CI20 board.
It also changes the nemc reg range to avoid overlap.
Tested-by: Mathieu Malaterre malat@debian.org Signed-off-by: PrasannaKumar Muralidharan prasannatsmkumar@gmail.com Signed-off-by: Mathieu Malaterre malat@debian.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com --- arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index f928329b034b..1e266be28096 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -358,7 +358,7 @@
nemc: nemc@13410000 { compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; + reg = <0x13410000 0x4c>; #address-cells = <2>; #size-cells = <1>; ranges = <1 0 0x1b000000 0x1000000 @@ -373,6 +373,21 @@ status = "disabled"; };
+ efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0x2c>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "ahb2"; + + #address-cells = <1>; + #size-cells = <1>; + + eth0_addr: eth-mac-addr@0x22 { + reg = <0x22 0x6>; + }; + }; + dma: dma@13420000 { compatible = "ingenic,jz4780-dma"; reg = <0x13420000 0x400
There is a unique MAC address programmed into the eFuses of the JZ4780 chip in the CI20 factory. By using this for initializing the DM9000 Ethernet controller, every CI20 board has an individual - but stable - MAC address and DHCP can assign stable IP addresses.
Signed-off-by: H. Nikolaus Schaller hns@goldelico.com --- arch/mips/boot/dts/ingenic/ci20.dts | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 37b93166bf22..6dc1f9eeff00 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -355,6 +355,9 @@
interrupt-parent = <&gpe>; interrupts = <19 4>; + + nvmem-cells = <ð0_addr>; + nvmem-cell-names = "mac-address"; }; };
-
Andreas Kemnade -
H. Nikolaus Schaller -
Paul Cercueil