Hi all,
Here's v2 of the pyra-4g ddr3 config. It's now a bit smaller set of changes, and igepv5 configuration is only used for interleaving.
With these changes and the related kernel dts change I can now run two instances of memtester 1900M after I added a heat sink to the CPU board :) It seems that when thermal starts reporting temperatures near 80 C, there can be memtester errors. To verify these really are thermal, I probably need to retest with a heatsink and a fan at some point.
Also when the device it hot, it seems u-boot is having hard time starting after a power cycle with errors like:
SDRAM: identified size not same as expected size identified: 0 expected: 40000000 WARNING: DDR RAM is not working! (12005678)
Waiting 10 - 20 seconds there seems to help with that.
Regards,
Tony
Tony Lindgren (3): Pyra/LC15: Workaround for 4GB DDR3 SMPS6 voltage Pyra/LC15: Fix up pyra-4g DDR3 configuration Pyra/LC15: Configure interleaving for 4GB DDR3
arch/arm/cpu/armv7/omap-common/emif-common.c | 5 +++ arch/arm/include/asm/emif.h | 1 + board/goldelico/letux-cortex15/lc15.c | 54 +++++++++++++++++++++++++--- include/palmas.h | 4 +++ 4 files changed, 60 insertions(+), 4 deletions(-)
Somehow we need 1.50V for the 4GB DDR3 to work reliably. No idea so far why this is though.
Note that we really should call pyra_set_ddr3_voltage() before sdram_init() but the i2c driver is not yet initialized in board_early_init_f().
If somebody wants to play with board_early_init_f(), please note that using it needs CONFIG_BOARD_EARLY_INIT_F enabled too. --- board/goldelico/letux-cortex15/lc15.c | 32 ++++++++++++++++++++++++++++++++ include/palmas.h | 4 ++++ 2 files changed, 36 insertions(+)
diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -248,6 +248,37 @@ static void simple_ram_test(void) printf("WARNING: DDR RAM is not working! (%x)\n", v[0]); }
+#ifdef CONFIG_DUAL_RANK_DDR3 +/* + * REVISIT: Somehow the 4GB K4B8G1646D-MYK0 part needs SMPS6 voltage + * set to 1.50V (0x6a) instead of 1.35V (0x5d). Values below 1.50V + * seem to be flakey. + */ +static void pyra_set_ddr3_voltage(void) +{ + int err; + + if (running_from_sdram()) + return; + + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, + SMPS6_VOLTAGE, 0x6a); + if (err) + goto err; + + mdelay(150); + + return; + +err: + printf("%s error: %i\n", __func__, err); +} +#else +static inline void pyra_set_ddr3_voltage(void) +{ +} +#endif + int board_mmc_init(bd_t *bis) { int hard_select = 7; /* gpio to select uSD (0) or eMMC (1) by external hw signal */ @@ -256,6 +287,7 @@ int board_mmc_init(bd_t *bis)
int val; /* is the value of soft_select gpio after processing */
+ pyra_set_ddr3_voltage(); simple_ram_test(); int vers = get_board_version(); #if 1 diff --git a/include/palmas.h b/include/palmas.h --- a/include/palmas.h +++ b/include/palmas.h @@ -60,6 +60,10 @@ /* Request bypass, LDO9 only */ #define LDO9_BYPASS 0x3f
+/* SMPS6_CTRL */ +#define SMPS6_CTRL 0x2c +#define SMPS6_VOLTAGE 0x2f + /* SMPS7_CTRL */ #define SMPS7_CTRL 0x30
* Tony Lindgren tony@atomide.com [170815 16:57]:
Somehow we need 1.50V for the 4GB DDR3 to work reliably. No idea so far why this is though.
And here's the related kernel dts change for 1.50V.
Tony
8< -----------------------
From tony Mon Sep 17 00:00:00 2001
From: Tony Lindgren tony@atomide.com Date: Tue, 15 Aug 2017 13:06:47 -0700 Subject: [PATCH] ARM: dts: Fix up DDR3 voltage for pyra 4G
Looks like we need 1.50V instead of 1.35V for pyra-4g DDR3 to work reliably. Note that this needs to match the voltage configured by the bootloader.
When testing memory with two instances of memtester 1900M for example, make sure ti-soc-thermal and thermal-generic-adc modules are loaded. You may also need to use a proper heat sink on the CPU board. --- arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi --- a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi +++ b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi @@ -816,6 +816,12 @@ vbus-supply = <&otg_reg>; };
+/* pyra-4g memory needs 1.50V instead of 1.35V somehow */ +&smps6_reg { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; +}; + &smps10_out1_reg { /* never turn on or it may burn the Palmas! */ status = "disabled";
On Di, 2017-08-15 at 17:00 -0700, Tony Lindgren wrote:
I just checked the part number on the 4GB RAM chips - and indeed, it is the K4B8G1646D, which means we have the DDR3 and NOT the DDR3L version (which would be K4B8G1646Q).
That's the reason we need 1.5V here. So we got the wrong memory chips for our use case!
I'll check back with what we ordered and what we received.
- Tony Lindgren tony@atomide.com [170815 16:57]:
Somehow we need 1.50V for the 4GB DDR3 to work reliably. No idea so far why this is though.
And here's the related kernel dts change for 1.50V.
Tony
8< -----------------------
From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren tony@atomide.com Date: Tue, 15 Aug 2017 13:06:47 -0700 Subject: [PATCH] ARM: dts: Fix up DDR3 voltage for pyra 4G
Looks like we need 1.50V instead of 1.35V for pyra-4g DDR3 to work reliably. Note that this needs to match the voltage configured by the bootloader.
When testing memory with two instances of memtester 1900M for example, make sure ti-soc-thermal and thermal-generic-adc modules are loaded. You may also need to use a proper heat sink on the CPU board.
arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi --- a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi +++ b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi @@ -816,6 +816,12 @@ vbus-supply = <&otg_reg>; };
+/* pyra-4g memory needs 1.50V instead of 1.35V somehow */ +&smps6_reg {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
+};
&smps10_out1_reg { /* never turn on or it may burn the Palmas! */ status = "disabled";
Okay... Now we have a bit of a problem.
Apparently,.as the memory was basically working but just freezing (we we thought was a software issue), we've ordered the memory already - we have 4000 of those chips in stock.
I'm now trying to find our whether we can exchange them (they're still untouched and sealed), but this might not work...
What downsides do we.have with DDR3 memory? How much more power.do they consume? How much more.heat do they produce?
Are there any other downsides?
On August 16, 2017 2:29:37 AM GMT+02:00, Michael Mrozek EvilDragon@openpandora.org wrote:
On Di, 2017-08-15 at 17:00 -0700, Tony Lindgren wrote:
I just checked the part number on the 4GB RAM chips - and indeed, it is the K4B8G1646D, which means we have the DDR3 and NOT the DDR3L version (which would be K4B8G1646Q).
That's the reason we need 1.5V here. So we got the wrong memory chips for our use case!
I'll check back with what we ordered and what we received.
- Tony Lindgren tony@atomide.com [170815 16:57]:
Somehow we need 1.50V for the 4GB DDR3 to work reliably. No idea so far why this is though.
And here's the related kernel dts change for 1.50V.
Tony
8< -----------------------
From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren tony@atomide.com Date: Tue, 15 Aug 2017 13:06:47 -0700 Subject: [PATCH] ARM: dts: Fix up DDR3 voltage for pyra 4G
Looks like we need 1.50V instead of 1.35V for pyra-4g DDR3 to work reliably. Note that this needs to match the voltage configured by the bootloader.
When testing memory with two instances of memtester 1900M for example, make sure ti-soc-thermal and thermal-generic-adc modules are loaded. You may also need to use a proper heat sink on the CPU board.
arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi --- a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi +++ b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi @@ -816,6 +816,12 @@ vbus-supply = <&otg_reg>; };
+/* pyra-4g memory needs 1.50V instead of 1.35V somehow */ +&smps6_reg {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
+};
&smps10_out1_reg { /* never turn on or it may burn the Palmas! */ status = "disabled";
-- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de/ HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org _______________________________________________ Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
Hi, according to my data sheets the K4B8G1646D is the DDR3L and the K4B8G1646Q isn't.
So please someone double-check before moving around chips&money.
So it is not the wrong chip but it might be too much noise on the data/clock/etc. which doubles for a dual-die/dual-chip-select chip. This gets better margin when increasing voltage levels.
Am 16.08.2017 um 09:32 schrieb Michael Mrozek EvilDragon@openpandora.org:
Okay... Now we have a bit of a problem.
Apparently,.as the memory was basically working but just freezing (we we thought was a software issue), we've ordered the memory already - we have 4000 of those chips in stock.
I'm now trying to find our whether we can exchange them (they're still untouched and sealed), but this might not work...
What downsides do we.have with DDR3 memory? How much more power.do http://power.do/ they consume? How much more.heat do they produce?
ignoring non-linear effects: (1.5V/1.35V)^2 = 1.23 i.e. 23% more.
Are there any other downsides?
A tiny one: we need separate DTB for 2GB and 4GB... But U-Boot can load the right one since we already have two different U-Boot binaries.
BR, Nikolaus
On August 16, 2017 2:29:37 AM GMT+02:00, Michael Mrozek EvilDragon@openpandora.org wrote: On Di, 2017-08-15 at 17:00 -0700, Tony Lindgren wrote:
I just checked the part number on the 4GB RAM chips - and indeed, it is the K4B8G1646D, which means we have the DDR3 and NOT the DDR3L version (which would be K4B8G1646Q).
That's the reason we need 1.5V here. So we got the wrong memory chips for our use case!
I'll check back with what we ordered and what we received.
- Tony Lindgren tony@atomide.com [170815 16:57]:
Somehow we need 1.50V for the 4GB DDR3 to work reliably. No idea so far why this is though.
And here's the related kernel dts change for 1.50V.
Tony
8< ----------------------- From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren tony@atomide.com Date: Tue, 15 Aug 2017 13:06:47 -0700 Subject: [PATCH] ARM: dts: Fix up DDR3 voltage for pyra 4G
Looks like we need 1.50V instead of 1.35V for pyra-4g DDR3 to work reliably. Note that this needs to match the voltage configured by the bootloader.
When testing memory with two instances of memtester 1900M for example, make sure ti-soc-thermal and thermal-generic-adc modules are loaded. You may also need to use a proper heat sink on the CPU board.
arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi --- a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi +++ b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi @@ -816,6 +816,12 @@ vbus-supply = <&otg_reg>; };
+/* pyra-4g memory needs 1.50V instead of 1.35V somehow */ +&smps6_reg {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
+};
&smps10_out1_reg { /* never turn on or it may burn the Palmas! */ status = "disabled"; -- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de http://www.openpandora.de// HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org
Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
-- Sent from my Android device with K-9 Mail. Please excuse my brevity. _______________________________________________ Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
On Mi, 2017-08-16 at 09:42 +0200, H. Nikolaus Schaller wrote:
Okay... it gets even more weird now.
Here is the K4B8G1646D as DDR3 (1,5V) variant: http://www.samsung.com/semiconductor/global/file/product/2016/06/DS_K4B 8G1646D_MC_Rev1_0-0.pdf
Here you can find it as DDR3L-variant: http://www.samsung.com/semiconductor/global/file/product/2016/03/DS_K4B 8G1646D-MY-M_Rev09-0.pdf
(this one explicitely says our ordered K4B8G1646D-MMK0 is DDR3L which supports 1,35V)
Then there is this product guide from Samsung: http://www.samsung.com/semiconductor/global/file/resourceMgmt/2016/11/D DR3_Product_guide_Oct.16[2]-0.pdf
Which basically says our chip is DDR3 with 1,5V.
According to our distributor, the chip we ordered and received should be DDR3L.
So... anyone has any idea what's wrong here? :O
Hi, according to my data sheets the K4B8G1646D is the DDR3L and the K4B8G1646Q isn't.
So please someone double-check before moving around chips&money.
So it is not the wrong chip but it might be too much noise on the data/clock/etc. which doubles for a dual-die/dual-chip-select chip. This gets better margin when increasing voltage levels.
Am 16.08.2017 um 09:32 schrieb Michael Mrozek <EvilDragon@openpando ra.org>:
Okay... Now we have a bit of a problem.
Apparently,.as the memory was basically working but just freezing (we we thought was a software issue), we've ordered the memory already - we have 4000 of those chips in stock.
I'm now trying to find our whether we can exchange them (they're still untouched and sealed), but this might not work...
What downsides do we.have with DDR3 memory? How much more power.do http://power.do/ they consume? How much more.heat do they produce?
ignoring non-linear effects: (1.5V/1.35V)^2 = 1.23 i.e. 23% more.
Are there any other downsides?
A tiny one: we need separate DTB for 2GB and 4GB... But U-Boot can load the right one since we already have two different U-Boot binaries.
BR, Nikolaus
On August 16, 2017 2:29:37 AM GMT+02:00, Michael Mrozek <EvilDragon @openpandora.org> wrote: On Di, 2017-08-15 at 17:00 -0700, Tony Lindgren wrote:
I just checked the part number on the 4GB RAM chips - and indeed, it is the K4B8G1646D, which means we have the DDR3 and NOT the DDR3L version (which would be K4B8G1646Q).
That's the reason we need 1.5V here. So we got the wrong memory chips for our use case!
I'll check back with what we ordered and what we received.
- Tony Lindgren tony@atomide.com [170815 16:57]:
Somehow we need 1.50V for the 4GB DDR3 to work reliably. No idea so far why this is though.
And here's the related kernel dts change for 1.50V.
Tony
8< ----------------------- From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren tony@atomide.com Date: Tue, 15 Aug 2017 13:06:47 -0700 Subject: [PATCH] ARM: dts: Fix up DDR3 voltage for pyra 4G
Looks like we need 1.50V instead of 1.35V for pyra-4g DDR3 to work reliably. Note that this needs to match the voltage configured by the bootloader.
When testing memory with two instances of memtester 1900M for example, make sure ti-soc-thermal and thermal-generic-adc modules are loaded. You may also need to use a proper heat sink on the CPU board.
arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi --- a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi +++ b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi @@ -816,6 +816,12 @@ vbus-supply = <&otg_reg>; };
+/* pyra-4g memory needs 1.50V instead of 1.35V somehow */ +&smps6_reg {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
+};
&smps10_out1_reg { /* never turn on or it may burn the Palmas! */ status = "disabled"; -- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de http://www.openpandora.de// HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org
Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel http://py ra-handheld.com/cgi-bin/mailman/listinfo/kernel
-- Sent from my Android device with K-9 Mail. Please excuse my brevity. _______________________________________________ Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
On Mi, 2017-08-16 at 10:20 +0200, Michael Mrozek wrote:
AAhh - I think I found my problem! I'm plain stupid!
That Samsung guide SAYS we have the low-power-version: http://www.samsung.com/semiconductor/global/file/resourceMgmt/2016/11/D DR3_Product_guide_Oct.16[2]-0.pdf
K4B8G1646Q-MMK0 IS 1,35V:) Industrial Temp.( -40C ~ 95C) & Low VDD(1.35V)
On first glance I saw the interface voltage, which is 1,5V.
Well... then it could be noise, though hopefully it isn't, as it would increase power consumption a lot!
On Mi, 2017-08-16 at 09:42 +0200, H. Nikolaus Schaller wrote:
Okay... it gets even more weird now.
Here is the K4B8G1646D as DDR3 (1,5V) variant: http://www.samsung.com/semiconductor/global/file/product/2016/06/DS_K 4B 8G1646D_MC_Rev1_0-0.pdf
Here you can find it as DDR3L-variant: http://www.samsung.com/semiconductor/global/file/product/2016/03/DS_K 4B 8G1646D-MY-M_Rev09-0.pdf
(this one explicitely says our ordered K4B8G1646D-MMK0 is DDR3L which supports 1,35V)
Then there is this product guide from Samsung: http://www.samsung.com/semiconductor/global/file/resourceMgmt/2016/11 /D DR3_Product_guide_Oct.16[2]-0.pdf
Which basically says our chip is DDR3 with 1,5V.
According to our distributor, the chip we ordered and received should be DDR3L.
So... anyone has any idea what's wrong here? :O
Hi, according to my data sheets the K4B8G1646D is the DDR3L and the K4B8G1646Q isn't.
So please someone double-check before moving around chips&money.
So it is not the wrong chip but it might be too much noise on the data/clock/etc. which doubles for a dual-die/dual-chip-select chip. This gets better margin when increasing voltage levels.
Am 16.08.2017 um 09:32 schrieb Michael Mrozek <EvilDragon@openpan do ra.org>:
Okay... Now we have a bit of a problem.
Apparently,.as the memory was basically working but just freezing (we we thought was a software issue), we've ordered the memory already - we have 4000 of those chips in stock.
I'm now trying to find our whether we can exchange them (they're still untouched and sealed), but this might not work...
What downsides do we.have with DDR3 memory? How much more power.do http://power.do/ they consume? How much more.heat do they produce?
ignoring non-linear effects: (1.5V/1.35V)^2 = 1.23 i.e. 23% more.
Are there any other downsides?
A tiny one: we need separate DTB for 2GB and 4GB... But U-Boot can load the right one since we already have two different U-Boot binaries.
BR, Nikolaus
On August 16, 2017 2:29:37 AM GMT+02:00, Michael Mrozek <EvilDragon @openpandora.org> wrote: On Di, 2017-08-15 at 17:00 -0700, Tony Lindgren wrote:
I just checked the part number on the 4GB RAM chips - and indeed, it is the K4B8G1646D, which means we have the DDR3 and NOT the DDR3L version (which would be K4B8G1646Q).
That's the reason we need 1.5V here. So we got the wrong memory chips for our use case!
I'll check back with what we ordered and what we received.
- Tony Lindgren tony@atomide.com [170815 16:57]:
Somehow we need 1.50V for the 4GB DDR3 to work reliably. No idea so far why this is though.
And here's the related kernel dts change for 1.50V.
Tony
8< ----------------------- From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren tony@atomide.com Date: Tue, 15 Aug 2017 13:06:47 -0700 Subject: [PATCH] ARM: dts: Fix up DDR3 voltage for pyra 4G
Looks like we need 1.50V instead of 1.35V for pyra-4g DDR3 to work reliably. Note that this needs to match the voltage configured by the bootloader.
When testing memory with two instances of memtester 1900M for example, make sure ti-soc-thermal and thermal-generic-adc modules are loaded. You may also need to use a proper heat sink on the CPU board.
arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi --- a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi +++ b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi @@ -816,6 +816,12 @@ vbus-supply = <&otg_reg>; };
+/* pyra-4g memory needs 1.50V instead of 1.35V somehow */ +&smps6_reg {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
+};
&smps10_out1_reg { /* never turn on or it may burn the Palmas! */ status = "disabled"; -- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de http://www.openpandora.de// HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org
Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel http:// py ra-handheld.com/cgi-bin/mailman/listinfo/kernel
-- Sent from my Android device with K-9 Mail. Please excuse my brevity. _______________________________________________ Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
Hi,
well this Samsung nomenclature is rather confusing. From what I understand: K4B8G1646D-MC* is DDR3 K4B8G1646D-MY* and K4B8G1646D-MM* is DDR3L.
So you have checked the actual markings and they're -MMK0? Tony's tests strongly suggest the chip wants full (not L) voltage for some reason. Could it be some of the samples sent were wrong? Can you check the markings on all 4G boards you have?
Other thing to check is the frequency, as it's DDR3L-1600 it should not be set over 800MHz.
Another interesting thing from the datasheet: The normal temperature is 0-85C (or -40-85 for industrial part). There is also "extended" temperature range of 85-95C which is supported, but requires refresh commands to be doubled in frequency. I don't know if OMAP5 can do that...
Tony reported crashes went away with a heatsink, so it seems to be heat related too.
Gražvydas
On Wed, Aug 16, 2017 at 11:58 AM, Michael Mrozek EvilDragon@openpandora.org wrote:
On Mi, 2017-08-16 at 10:20 +0200, Michael Mrozek wrote:
AAhh - I think I found my problem! I'm plain stupid!
That Samsung guide SAYS we have the low-power-version: http://www.samsung.com/semiconductor/global/file/resourceMgmt/2016/11/D DR3_Product_guide_Oct.16[2]-0.pdf
K4B8G1646Q-MMK0 IS 1,35V:) Industrial Temp.( -40C ~ 95C) & Low VDD(1.35V)
On first glance I saw the interface voltage, which is 1,5V.
Well... then it could be noise, though hopefully it isn't, as it would increase power consumption a lot!
On Mi, 2017-08-16 at 09:42 +0200, H. Nikolaus Schaller wrote:
Okay... it gets even more weird now.
Here is the K4B8G1646D as DDR3 (1,5V) variant: http://www.samsung.com/semiconductor/global/file/product/2016/06/DS_K 4B 8G1646D_MC_Rev1_0-0.pdf
Here you can find it as DDR3L-variant: http://www.samsung.com/semiconductor/global/file/product/2016/03/DS_K 4B 8G1646D-MY-M_Rev09-0.pdf
(this one explicitely says our ordered K4B8G1646D-MMK0 is DDR3L which supports 1,35V)
Then there is this product guide from Samsung: http://www.samsung.com/semiconductor/global/file/resourceMgmt/2016/11 /D DR3_Product_guide_Oct.16[2]-0.pdf
Which basically says our chip is DDR3 with 1,5V.
According to our distributor, the chip we ordered and received should be DDR3L.
So... anyone has any idea what's wrong here? :O
Hi, according to my data sheets the K4B8G1646D is the DDR3L and the K4B8G1646Q isn't.
So please someone double-check before moving around chips&money.
So it is not the wrong chip but it might be too much noise on the data/clock/etc. which doubles for a dual-die/dual-chip-select chip. This gets better margin when increasing voltage levels.
Am 16.08.2017 um 09:32 schrieb Michael Mrozek <EvilDragon@openpan do ra.org>:
Okay... Now we have a bit of a problem.
Apparently,.as the memory was basically working but just freezing (we we thought was a software issue), we've ordered the memory already - we have 4000 of those chips in stock.
I'm now trying to find our whether we can exchange them (they're still untouched and sealed), but this might not work...
What downsides do we.have with DDR3 memory? How much more power.do http://power.do/ they consume? How much more.heat do they produce?
ignoring non-linear effects: (1.5V/1.35V)^2 = 1.23 i.e. 23% more.
Are there any other downsides?
A tiny one: we need separate DTB for 2GB and 4GB... But U-Boot can load the right one since we already have two different U-Boot binaries.
BR, Nikolaus
On August 16, 2017 2:29:37 AM GMT+02:00, Michael Mrozek <EvilDragon @openpandora.org> wrote: On Di, 2017-08-15 at 17:00 -0700, Tony Lindgren wrote:
I just checked the part number on the 4GB RAM chips - and indeed, it is the K4B8G1646D, which means we have the DDR3 and NOT the DDR3L version (which would be K4B8G1646Q).
That's the reason we need 1.5V here. So we got the wrong memory chips for our use case!
I'll check back with what we ordered and what we received.
- Tony Lindgren tony@atomide.com [170815 16:57]:
Somehow we need 1.50V for the 4GB DDR3 to work reliably. No idea so far why this is though.
And here's the related kernel dts change for 1.50V.
Tony
8< ----------------------- From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren tony@atomide.com Date: Tue, 15 Aug 2017 13:06:47 -0700 Subject: [PATCH] ARM: dts: Fix up DDR3 voltage for pyra 4G
Looks like we need 1.50V instead of 1.35V for pyra-4g DDR3 to work reliably. Note that this needs to match the voltage configured by the bootloader.
When testing memory with two instances of memtester 1900M for example, make sure ti-soc-thermal and thermal-generic-adc modules are loaded. You may also need to use a proper heat sink on the CPU board.
arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi --- a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi +++ b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi @@ -816,6 +816,12 @@ vbus-supply = <&otg_reg>; };
+/* pyra-4g memory needs 1.50V instead of 1.35V somehow */ +&smps6_reg {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
+};
&smps10_out1_reg { /* never turn on or it may burn the Palmas! */ status = "disabled"; -- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de http://www.openpandora.de// HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org
Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel http:// py ra-handheld.com/cgi-bin/mailman/listinfo/kernel
-- Sent from my Android device with K-9 Mail. Please excuse my brevity. _______________________________________________ Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
-- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de/ HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org _______________________________________________ Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
Am Mittwoch, den 16.08.2017, 14:10 +0300 schrieb Grazvydas Ignotas:
Hi,
well this Samsung nomenclature is rather confusing. From what I understand: K4B8G1646D-MC* is DDR3 K4B8G1646D-MY* and K4B8G1646D-MM* is DDR3L. So you have checked the actual markings and they're -MMK0?
Yes. At least on the CPU Board I checked, they're all MMK0.
Tony's tests strongly suggest the chip wants full (not L) voltage for some reason. Could it be some of the samples sent were wrong? Can you check the markings on all 4G boards you have?
I will check them later. @Tony: Could you also check yours?
Other thing to check is the frequency, as it's DDR3L-1600 it should not be set over 800MHz.
Yes, I think Mathijs wanted to look at that, but didn't yet.
Another interesting thing from the datasheet: The normal temperature is 0-85C (or -40-85 for industrial part). There is also "extended" temperature range of 85-95C which is supported, but requires refresh commands to be doubled in frequency. I don't know if OMAP5 can do that...
Ah, okay! Well, we should add proper throttle values into the DT file anyways. I think the OMAP shouldn't go higher than 80C while using it.
Tony reported crashes went away with a heatsink, so it seems to be heat related too.
Gražvydas
On Wed, Aug 16, 2017 at 11:58 AM, Michael Mrozek EvilDragon@openpandora.org wrote:
On Mi, 2017-08-16 at 10:20 +0200, Michael Mrozek wrote:
AAhh - I think I found my problem! I'm plain stupid!
That Samsung guide SAYS we have the low-power-version: http://www.samsung.com/semiconductor/global/file/resourceMgmt/2016/ 11/D DR3_Product_guide_Oct.16[2]-0.pdf
K4B8G1646Q-MMK0 IS 1,35V:) Industrial Temp.( -40C ~ 95C) & Low VDD(1.35V)
On first glance I saw the interface voltage, which is 1,5V.
Well... then it could be noise, though hopefully it isn't, as it would increase power consumption a lot!
On Mi, 2017-08-16 at 09:42 +0200, H. Nikolaus Schaller wrote:
Okay... it gets even more weird now.
Here is the K4B8G1646D as DDR3 (1,5V) variant: http://www.samsung.com/semiconductor/global/file/product/2016/06/ DS_K 4B 8G1646D_MC_Rev1_0-0.pdf
Here you can find it as DDR3L-variant: http://www.samsung.com/semiconductor/global/file/product/2016/03/ DS_K 4B 8G1646D-MY-M_Rev09-0.pdf
(this one explicitely says our ordered K4B8G1646D-MMK0 is DDR3L which supports 1,35V)
Then there is this product guide from Samsung: http://www.samsung.com/semiconductor/global/file/resourceMgmt/201 6/11 /D DR3_Product_guide_Oct.16[2]-0.pdf
Which basically says our chip is DDR3 with 1,5V.
According to our distributor, the chip we ordered and received should be DDR3L.
So... anyone has any idea what's wrong here? :O
Hi, according to my data sheets the K4B8G1646D is the DDR3L and the K4B8G1646Q isn't.
So please someone double-check before moving around chips&money.
So it is not the wrong chip but it might be too much noise on the data/clock/etc. which doubles for a dual-die/dual-chip-select chip. This gets better margin when increasing voltage levels.
Am 16.08.2017 um 09:32 schrieb Michael Mrozek <EvilDragon@ope npan do ra.org>:
Okay... Now we have a bit of a problem.
Apparently,.as the memory was basically working but just freezing (we we thought was a software issue), we've ordered the memory already - we have 4000 of those chips in stock.
I'm now trying to find our whether we can exchange them (they're still untouched and sealed), but this might not work...
What downsides do we.have with DDR3 memory? How much more power.do http://power.do/ they consume? How much more.heat do they produce?
ignoring non-linear effects: (1.5V/1.35V)^2 = 1.23 i.e. 23% more.
Are there any other downsides?
A tiny one: we need separate DTB for 2GB and 4GB... But U-Boot can load the right one since we already have two different U-Boot binaries.
BR, Nikolaus
On August 16, 2017 2:29:37 AM GMT+02:00, Michael Mrozek <EvilDragon @openpandora.org> wrote: On Di, 2017-08-15 at 17:00 -0700, Tony Lindgren wrote:
I just checked the part number on the 4GB RAM chips - and indeed, it is the K4B8G1646D, which means we have the DDR3 and NOT the DDR3L version (which would be K4B8G1646Q).
That's the reason we need 1.5V here. So we got the wrong memory chips for our use case!
I'll check back with what we ordered and what we received.
- Tony Lindgren tony@atomide.com [170815 16:57]:
Somehow we need 1.50V for the 4GB DDR3 to work reliably. No idea so far why this is though.
And here's the related kernel dts change for 1.50V.
Tony
8< ----------------------- From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren tony@atomide.com Date: Tue, 15 Aug 2017 13:06:47 -0700 Subject: [PATCH] ARM: dts: Fix up DDR3 voltage for pyra 4G
Looks like we need 1.50V instead of 1.35V for pyra-4g DDR3 to work reliably. Note that this needs to match the voltage configured by the bootloader.
When testing memory with two instances of memtester 1900M for example, make sure ti-soc-thermal and thermal-generic- adc modules are loaded. You may also need to use a proper heat sink on the CPU board.
arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi --- a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi +++ b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi @@ -816,6 +816,12 @@ vbus-supply = <&otg_reg>; };
+/* pyra-4g memory needs 1.50V instead of 1.35V somehow */ +&smps6_reg {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
+};
&smps10_out1_reg { /* never turn on or it may burn the Palmas! */ status = "disabled"; -- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de http://www.openpandora.de// HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org
Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel http:// py ra-handheld.com/cgi-bin/mailman/listinfo/kernel
-- Sent from my Android device with K-9 Mail. Please excuse my brevity. _______________________________________________ Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
-- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de/ HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org _______________________________________________ Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
Hi, I found some minutes to run a quick test with 4.13-rc5. I just increased kernel SMPS6 setting to 1.5V and changed nothing else.
It does still not boot very well.
I see on first attempt:
[ 2.613219] smps6: Bringing 1350000uV into 1500000-1500000uV
but it has no visible effects before or after.
3 (!) seconds later I see the first symptom of something going wrong:
[ 5.872657] WARNING: suspicious RCU usage
And 2 more seconds later:
[ 7.876792] Alignment trap: not handling instruction e1953f9f at [<c08410f8>] [ 7.901314] Unhandled fault: alignment exception (0x221) at 0x000017ff
ending in a kernel panic. So this is 5 seconds after raising the memory voltage making it difficult to explain why memory voltage should have such an influence.
On some other attempts to boot, the kernel (and console echo) simply hangs after printing "Synthesizing the initial hotplug events".
And I was not able to boot successfully.
Well, the kernel image loaded by 1.35V U-Boot could flip some bits until needed... So I should better mix with U-Boot 1.5V patches. But I can do that only after next week.
BTW: still in the log: [ 2.218885] BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1 [ 2.227195] caller is pwrdm_set_next_pwrst+0x48/0x1d8 [ 2.232548] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.13.0-rc5-letux-lpae+ #1330 [ 2.240484] Hardware name: Generic OMAP5 (Flattened Device Tree) [ 2.246791] [<c020eae0>] (unwind_backtrace) from [<c020afec>] (show_stack+0x10/0x14) [ 2.254923] [<c020afec>] (show_stack) from [<c084bf48>] (dump_stack+0x98/0xd0) [ 2.262501] [<c084bf48>] (dump_stack) from [<c055254c>] (check_preemption_disabled+0xec/0x124) [ 2.271532] [<c055254c>] (check_preemption_disabled) from [<c02203b8>] (pwrdm_set_next_pwrst+0x48/0x1d8) [ 2.281482] [<c02203b8>] (pwrdm_set_next_pwrst) from [<c0e0cdf0>] (omap4_mpuss_init+0xb4/0x23c) [ 2.290612] [<c0e0cdf0>] (omap4_mpuss_init) from [<c0e0d20c>] (omap4_pm_init+0xf4/0x160) [ 2.299096] [<c0e0d20c>] (omap4_pm_init) from [<c0e0a414>] (omap5_init_late+0x10/0x18) [ 2.307407] [<c0e0a414>] (omap5_init_late) from [<c0e03560>] (init_machine_late+0x1c/0x90) [ 2.316081] [<c0e03560>] (init_machine_late) from [<c02018d8>] (do_one_initcall+0xa8/0x150) [ 2.324852] [<c02018d8>] (do_one_initcall) from [<c0e00d94>] (kernel_init_freeable+0x110/0x1d4) [ 2.333984] [<c0e00d94>] (kernel_init_freeable) from [<c085d578>] (kernel_init+0x8/0x10c) [ 2.342567] [<c085d578>] (kernel_init) from [<c0206ee8>] (ret_from_fork+0x14/0x2c) [ 2.350590] BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1 [ 2.354415] ata1: SATA link down (SStatus 0 SControl 300) [ 2.364553] caller is pwrdm_set_next_pwrst+0x48/0x1d8 [ 2.369852] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.13.0-rc5-letux-lpae+ #1330 [ 2.377786] Hardware name: Generic OMAP5 (Flattened Device Tree) [ 2.384090] [<c020eae0>] (unwind_backtrace) from [<c020afec>] (show_stack+0x10/0x14) [ 2.392210] [<c020afec>] (show_stack) from [<c084bf48>] (dump_stack+0x98/0xd0) [ 2.399786] [<c084bf48>] (dump_stack) from [<c055254c>] (check_preemption_disabled+0xec/0x124) [ 2.408825] [<c055254c>] (check_preemption_disabled) from [<c02203b8>] (pwrdm_set_next_pwrst+0x48/0x1d8) [ 2.418765] [<c02203b8>] (pwrdm_set_next_pwrst) from [<c0e0ce6c>] (omap4_mpuss_init+0x130/0x23c) [ 2.427978] [<c0e0ce6c>] (omap4_mpuss_init) from [<c0e0d20c>] (omap4_pm_init+0xf4/0x160) [ 2.436464] [<c0e0d20c>] (omap4_pm_init) from [<c0e0a414>] (omap5_init_late+0x10/0x18) [ 2.444775] [<c0e0a414>] (omap5_init_late) from [<c0e03560>] (init_machine_late+0x1c/0x90) [ 2.453448] [<c0e03560>] (init_machine_late) from [<c02018d8>] (do_one_initcall+0xa8/0x150) [ 2.462218] [<c02018d8>] (do_one_initcall) from [<c0e00d94>] (kernel_init_freeable+0x110/0x1d4) [ 2.471346] [<c0e00d94>] (kernel_init_freeable) from [<c085d578>] (kernel_init+0x8/0x10c) [ 2.479925] [<c085d578>] (kernel_init) from [<c0206ee8>] (ret_from_fork+0x14/0x2c)
Hope this is useful info.
BR, Nikolaus
Am 16.08.2017 um 13:27 schrieb Michael Mrozek EvilDragon@openpandora.org:
Am Mittwoch, den 16.08.2017, 14:10 +0300 schrieb Grazvydas Ignotas:
Hi,
well this Samsung nomenclature is rather confusing. From what I understand: K4B8G1646D-MC* is DDR3 K4B8G1646D-MY* and K4B8G1646D-MM* is DDR3L. So you have checked the actual markings and they're -MMK0?
Yes. At least on the CPU Board I checked, they're all MMK0.
Tony's tests strongly suggest the chip wants full (not L) voltage for some reason. Could it be some of the samples sent were wrong? Can you check the markings on all 4G boards you have?
I will check them later. @Tony: Could you also check yours?
Other thing to check is the frequency, as it's DDR3L-1600 it should not be set over 800MHz.
Yes, I think Mathijs wanted to look at that, but didn't yet.
Another interesting thing from the datasheet: The normal temperature is 0-85C (or -40-85 for industrial part). There is also "extended" temperature range of 85-95C which is supported, but requires refresh commands to be doubled in frequency. I don't know if OMAP5 can do that...
Ah, okay! Well, we should add proper throttle values into the DT file anyways. I think the OMAP shouldn't go higher than 80C while using it.
Tony reported crashes went away with a heatsink, so it seems to be heat related too.
Gražvydas
On Wed, Aug 16, 2017 at 11:58 AM, Michael Mrozek EvilDragon@openpandora.org wrote:
On Mi, 2017-08-16 at 10:20 +0200, Michael Mrozek wrote:
AAhh - I think I found my problem! I'm plain stupid!
That Samsung guide SAYS we have the low-power-version: http://www.samsung.com/semiconductor/global/file/resourceMgmt/2016/ 11/D DR3_Product_guide_Oct.16[2]-0.pdf
K4B8G1646Q-MMK0 IS 1,35V:) Industrial Temp.( -40C ~ 95C) & Low VDD(1.35V)
On first glance I saw the interface voltage, which is 1,5V.
Well... then it could be noise, though hopefully it isn't, as it would increase power consumption a lot!
On Mi, 2017-08-16 at 09:42 +0200, H. Nikolaus Schaller wrote:
Okay... it gets even more weird now.
Here is the K4B8G1646D as DDR3 (1,5V) variant: http://www.samsung.com/semiconductor/global/file/product/2016/06/ DS_K 4B 8G1646D_MC_Rev1_0-0.pdf
Here you can find it as DDR3L-variant: http://www.samsung.com/semiconductor/global/file/product/2016/03/ DS_K 4B 8G1646D-MY-M_Rev09-0.pdf
(this one explicitely says our ordered K4B8G1646D-MMK0 is DDR3L which supports 1,35V)
Then there is this product guide from Samsung: http://www.samsung.com/semiconductor/global/file/resourceMgmt/201 6/11 /D DR3_Product_guide_Oct.16[2]-0.pdf
Which basically says our chip is DDR3 with 1,5V.
According to our distributor, the chip we ordered and received should be DDR3L.
So... anyone has any idea what's wrong here? :O
Hi, according to my data sheets the K4B8G1646D is the DDR3L and the K4B8G1646Q isn't.
So please someone double-check before moving around chips&money.
So it is not the wrong chip but it might be too much noise on the data/clock/etc. which doubles for a dual-die/dual-chip-select chip. This gets better margin when increasing voltage levels.
Am 16.08.2017 um 09:32 schrieb Michael Mrozek <EvilDragon@ope npan do ra.org>:
Okay... Now we have a bit of a problem.
Apparently,.as the memory was basically working but just freezing (we we thought was a software issue), we've ordered the memory already - we have 4000 of those chips in stock.
I'm now trying to find our whether we can exchange them (they're still untouched and sealed), but this might not work...
What downsides do we.have with DDR3 memory? How much more power.do http://power.do/ they consume? How much more.heat do they produce?
ignoring non-linear effects: (1.5V/1.35V)^2 = 1.23 i.e. 23% more.
Are there any other downsides?
A tiny one: we need separate DTB for 2GB and 4GB... But U-Boot can load the right one since we already have two different U-Boot binaries.
BR, Nikolaus
On August 16, 2017 2:29:37 AM GMT+02:00, Michael Mrozek <EvilDragon @openpandora.org> wrote: On Di, 2017-08-15 at 17:00 -0700, Tony Lindgren wrote:
I just checked the part number on the 4GB RAM chips - and indeed, it is the K4B8G1646D, which means we have the DDR3 and NOT the DDR3L version (which would be K4B8G1646Q).
That's the reason we need 1.5V here. So we got the wrong memory chips for our use case!
I'll check back with what we ordered and what we received.
- Tony Lindgren tony@atomide.com [170815 16:57]:
Somehow we need 1.50V for the 4GB DDR3 to work reliably. No idea so far why this is though.
And here's the related kernel dts change for 1.50V.
Tony
8< ----------------------- From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren tony@atomide.com Date: Tue, 15 Aug 2017 13:06:47 -0700 Subject: [PATCH] ARM: dts: Fix up DDR3 voltage for pyra 4G
Looks like we need 1.50V instead of 1.35V for pyra-4g DDR3 to work reliably. Note that this needs to match the voltage configured by the bootloader.
When testing memory with two instances of memtester 1900M for example, make sure ti-soc-thermal and thermal-generic- adc modules are loaded. You may also need to use a proper heat sink on the CPU board.
arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi --- a/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi +++ b/arch/arm/boot/dts/pyra-mainboard-v5.0.dtsi @@ -816,6 +816,12 @@ vbus-supply = <&otg_reg>; };
+/* pyra-4g memory needs 1.50V instead of 1.35V somehow */ +&smps6_reg {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
+};
&smps10_out1_reg { /* never turn on or it may burn the Palmas! */ status = "disabled"; -- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de http://www.openpandora.de// HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org
Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel http:// py ra-handheld.com/cgi-bin/mailman/listinfo/kernel
-- Sent from my Android device with K-9 Mail. Please excuse my brevity. _______________________________________________ Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
-- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de/ HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org _______________________________________________ Kernel mailing list Kernel@pyra-handheld.com http://pyra-handheld.com/cgi-bin/mailman/listinfo/kernel
-- Mit freundlichen Grüßen,
Michael Mrozek
OpenPandora GmbH Geschäftsführer: Michael Mrozek
Schäffbräustr. 11 85049 Ingolstadt Deutschland Tel.: 0841 / 990 5548 http://www.openpandora.de/ HRB 4879, Amtsgericht Ingolstadt
eMail: mrozek@openpandora.org
On Wed, Aug 16, 2017 at 4:00 PM, H. Nikolaus Schaller hns@goldelico.com wrote:
Hi, I found some minutes to run a quick test with 4.13-rc5. I just increased kernel SMPS6 setting to 1.5V and changed nothing else.
It does still not boot very well.
I see on first attempt:
[ 2.613219] smps6: Bringing 1350000uV into 1500000-1500000uV
but it has no visible effects before or after.
From what I understood from Tony, you need the termination and
interleave settings too to get any improvement (3 u-boot patches sent today).
Gražvydas
Ah ok. So we have multiple reasons for single problem. Tnx, Nikolaus.
On the road.
Am 16.08.2017 um 15:17 schrieb Grazvydas Ignotas notasas@gmail.com:
On Wed, Aug 16, 2017 at 4:00 PM, H. Nikolaus Schaller hns@goldelico.com wrote:
Hi, I found some minutes to run a quick test with 4.13-rc5. I just increased kernel SMPS6 setting to 1.5V and changed nothing else.
It does still not boot very well.
I see on first attempt:
[ 2.613219] smps6: Bringing 1350000uV into 1500000-1500000uV
but it has no visible effects before or after.
From what I understood from Tony, you need the termination and interleave settings too to get any improvement (3 u-boot patches sent today).
Gražvydas
* Grazvydas Ignotas notasas@gmail.com [170816 06:17]:
On Wed, Aug 16, 2017 at 4:00 PM, H. Nikolaus Schaller hns@goldelico.com wrote:
Hi, I found some minutes to run a quick test with 4.13-rc5. I just increased kernel SMPS6 setting to 1.5V and changed nothing else.
It does still not boot very well.
I see on first attempt:
[ 2.613219] smps6: Bringing 1350000uV into 1500000-1500000uV
but it has no visible effects before or after.
From what I understood from Tony, you need the termination and interleave settings too to get any improvement (3 u-boot patches sent today).
Correct, so far it seems all three u-boot patches plus the related kernel dts patch are needed.
Regards,
Tony
* Michael Mrozek EvilDragon@openpandora.org [170816 04:27]:
Am Mittwoch, den 16.08.2017, 14:10 +0300 schrieb Grazvydas Ignotas:
Hi,
well this Samsung nomenclature is rather confusing. From what I understand: K4B8G1646D-MC* is DDR3 K4B8G1646D-MY* and K4B8G1646D-MM* is DDR3L. So you have checked the actual markings and they're -MMK0?
Yes. At least on the CPU Board I checked, they're all MMK0.
Tony's tests strongly suggest the chip wants full (not L) voltage for some reason. Could it be some of the samples sent were wrong? Can you check the markings on all 4G boards you have?
I will check them later. @Tony: Could you also check yours?
I have this on mine:
SEC813 K4B8G16 46DMMK0
So yeah claims to be -MMK0 but then again the print could be wrong..
Regards,
Tony
Am Wed, 16 Aug 2017 07:38:18 -0700 hat Tony Lindgren tony@atomide.com geschrieben:
Hi,
while it's possible, I dont think the prints are wrong... It seems unlikely to me.
Have we already played around with the Frequency? What speed are they currently set to?
markings on all 4G boards you have?
I will check them later. @Tony: Could you also check yours?
I have this on mine:
SEC813 K4B8G16 46DMMK0
So yeah claims to be -MMK0 but then again the print could be wrong..
Regards,
Tony
Based on my brief testing, no termination works with Matthij's timings on pyra-4g as suggested by Matthijs van Duin matthijsvanduin@gmail.com.
Without this patch, u-boot has hard time starting reliably even with smps6 set to 1.50V and interleaving configured. --- board/goldelico/letux-cortex15/lc15.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -37,8 +37,8 @@ const struct omap_sysinfo sysinfo = { */
const struct emif_regs emif_regs_ddr3_532_mhz_2cs_es2 = { - .sdram_config_init = 0x61851B3A, - .sdram_config = 0x61851B3A, + .sdram_config_init = 0x60851B3A, + .sdram_config = 0x60851B3A, .sdram_config2 = 0x0, .ref_ctrl = 0x00001035, .sdram_tim1 = 0xCCCF36B3,
Based on igepv5 u-boot commit 4521f304a913 ("IGEPv5: Modify lisa_regs structure, added ma_hm_interleave variable") by Manel Caro mcaro@iseebcn.com, we need to configure interleaving for 4GB DDR3 to work properly.
With out this patch u-boot somehow has hard time booting reliably even with smps6 set to 1.50V and termination set to 0.
Note that with interleaving the memory addresses are different if passed from kernel command line. Typically those can be left out as u-boot will pass them. --- arch/arm/cpu/armv7/omap-common/emif-common.c | 5 +++++ arch/arm/include/asm/emif.h | 1 + board/goldelico/letux-cortex15/lc15.c | 18 ++++++++++++++++-- 3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1339,6 +1339,11 @@ void dmm_init(u32 base) &hw_lisa_map_regs->dmm_lisa_map_0);
setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); + + /* MA_PRIORITY[8] HIMEM_INTERLEAVE_UN bit to 0x1 */ + if (lisa_map_regs->is_ma_hm_interleave) + __raw_writel(__raw_readl(MA_PRIORITY) | + (1 << 8) , MA_PRIORITY); }
/* diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -756,6 +756,7 @@ struct dmm_lisa_map_regs { u32 dmm_lisa_map_2; u32 dmm_lisa_map_3; u8 is_ma_present; + u8 is_ma_hm_interleave; };
#define CS0 0 diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -66,10 +66,10 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) }
void dram_init_banksize(void) -{ /* make U-Boot pass the same as bootarg "mem=2032M@0x80000000 mem=2048M@0x200000000" would do */ +{ /* make U-Boot pass the same as bootarg "mem=2032M@0x80000000 mem=2048M@0x300000000" would do */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; // == 0x80000000 gd->bd->bi_dram[0].size = 2032*(1024UL*1024); // first 2GB - gd->bd->bi_dram[1].start = 0x200000000UL; + gd->bd->bi_dram[1].start = 0x300000000UL; gd->bd->bi_dram[1].size = 2048*(1024UL*1024); // second 2GB #if 0 // get back "stolen" memory gd->bd->bi_dram[1].start = 0x2FF000000UL; @@ -78,6 +78,20 @@ void dram_init_banksize(void) /* report 4 GB during boot */ gd->ram_size = gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size; } + +const struct dmm_lisa_map_regs lisa_map_pyra_4g = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x807C0300, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1, + .is_ma_hm_interleave = 0x1, +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &lisa_map_pyra_4g; +} #endif
/*
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Dr. H. Nikolaus Schaller -
Grazvydas Ignotas -
H. Nikolaus Schaller
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Michael Mrozek -
Tony Lindgren