Hi Nikolaus!
EvilDragon has told that there is 4 GB RAM prototype around, but it has special issue: "... it needs to have the RAM timings, etc. setup in bootup and kernel, otherwise, the kernel simply crashes."
I don't recall anything about it in maillists or in introductions from you. Could you please give some specific hints about actual state and what should be done? What can be done, with and without the prototype on hands?
Hi Andrey,
Am 06.07.2016 um 15:19 schrieb Andrey Utkin andrey_utkin@fastmail.com:
Hi Nikolaus!
EvilDragon has told that there is 4 GB RAM prototype around, but it has special issue: "... it needs to have the RAM timings, etc. setup in bootup and kernel, otherwise, the kernel simply crashes."
I don't recall anything about it in maillists or in introductions from you. Could you please give some specific hints about actual state and what should be done? What can be done, with and without the prototype on hands?
The basic 2GB Pyra is exactly as the OMAP5432EVM is set up. So the bootloaders and kernel needs no tweaking for DRAM.
This means 2 RAM chips (one die and 16 bits each) are connected to each of the two 32 bit EMIF ports. This means each port uses just one chip-select since there is nothing to select...
Now with 4 GB RAM we will have the same number of chips but two dies are connected in parallel in each chip package. Except that their chip-select pins are routed to the two separate chip select outputs of each EMIF port.
I.e. there are two set of RAM dies connected in parallel and we need to make the OMAP5 choose different chip selects so that either set responds and gives 4 GB RAM. Since 4 GB can't be mapped into physical address space this must somehow be connected to the virtual memory management.
MLO/Xloader (now called U-Boot SPL) should run and indeed does by simply ignoring the second chip select. So it will only see half of the dies and reports 2 GB RAM.
The kernel seems to make its own initializations and adjustments to the EMIF and there it should enable/control the second bank of RAM dies.
This means there are two areas to tell the OMAP how the RAM is organised:
a) http://git.goldelico.com/?p=gta04-uboot.git;a=blob;f=arch/arm/cpu/armv7/omap... http://git.goldelico.com/?p=gta04-uboot.git;a=blob;f=arch/arm/cpu/armv7/omap...
This probably does not need modifications - unless the kernel relies on the setup made there.
b) somewhere in the kernel (but in an area that I don't understand at all)
The status is that we have one CPU board (#C12) where two of the DRAM chips have been replaced by those with double capacity, i.e. it has 3GB RAM installed. But shows and uses only 2 GB - which is expected.
But the kernel hangs after ~5 seconds.
This might either be because the second RAM bank isn't working at all in kernel mode. Or not properly. Or the chip select is floating and makes the other bank fail. Or even something else broken by soldering different RAM chips. I don't know.
Hope this helps to start do dig into this topic. If you need more information please ask!
BR, Nikolaus
On Wed, Jul 06, 2016 at 03:45:40PM +0200, H. Nikolaus Schaller wrote:
Hope this helps to start do dig into this topic. If you need more information please ask!
Thanks for great introduction. Lazy man's question: are TI engineers who help us aware of this? Is it worth asking them about this?
On 07/06/2016 04:02 PM, Andrey Utkin wrote:
On Wed, Jul 06, 2016 at 03:45:40PM +0200, H. Nikolaus Schaller wrote:
Hope this helps to start do dig into this topic. If you need more information please ask!
Thanks for great introduction. Lazy man's question: are TI engineers who help us aware of this? Is it worth asking them about this?
IGEP have an omap5432 board with 4GB of ram, so it should work. Maybe there are some clues in their kernel/u-boot.
Am 06.07.2016 um 16:02 schrieb Andrey Utkin andrey_utkin@fastmail.com:
On Wed, Jul 06, 2016 at 03:45:40PM +0200, H. Nikolaus Schaller wrote:
Hope this helps to start do dig into this topic. If you need more information please ask!
Thanks for great introduction. Lazy man's question: are TI engineers who help us aware of this?
Tony can probably help us (although he is not TI engineer).
Is it worth asking them about this?
AFAIK the EMIF of the DRA7xx / AM5xxx (Beagleboard X15) and other A15 chipsets are similar or even the same.
So we might find a board with >2GB RAM and look how they are doing it.
BR, Nikolaus