On Do, 2018-09-20 at 09:29 -0700, Tony Lindgren wrote:
Also, simply comparing the values to the datasheet might help as well.
Yes please do check again :)
Just tried doing that, I have a few questions though:
1. Is there an EMIF-Tool for the OMAP5 as well? I only found the EMIF RegisterConfig Rev 2.0.1 (which is for the DRA7 and similar. The one I used is this one: http://www.ti.com/lit/an/sprac36b/sprac36b.zip
2. Table 1 (Step1-SystemDetails) requires system details like ODT, Output Driver Impedance, etc. Aren't these dependant on our board layout? How can we get these? It says "** NOTE: IBIS models should be used for signal integrity analysis. I/O settings programmed should match simulation settings."... so can we get these values from Juliano?
3. Does the OMAP5 support Hardware Levelling and have we enabled that? Otherwise, we need the trace lengths (according to Step2-BoardDetails).
4. On Step3-DDRTimings, most timings are already exactly like they say in our datasheet. Some values are "minimum" or "maximum". Are these values we can play around with to give the RAM a bit more safety?
5.As mentioned, those specs are exactly the same as in our datasheet. Howeve, I noticed that tfRAW has the value 50 pre-setup in the tool (which is for 2KB page size) whereas the value tRRD has the value 7.5 pre-setup in the tool (which is for 1KB page size). Is that a mismatch or doesn't that matter?
6. Some values the tool spits out are different than what we have in U- Boot. Some examples: .sdram_config and .sdram_config_init: 0x61851BB2 in the EMIF tool, 0x61851B3A in U-Boot.
.sdram_tim1 is 0xCCCF36B5 according to the EMIF Tool, but we use 0xCCCF36B3 (so a bit lower).
.emif_ddr_phy_ctlr_1_init is 0x0024400B in the EMIF Tool, but we are using 0x0030400A.
.emif_rd_wr_exec_thresh is 0x00000305 in the EMIF Tool, we're using 0x40000305
.zq_config results in 0x5007190B and we're using 0xD007190B,
So yeah, there ARE some differences - though I have no idea what these values mean. Do they have something to do with those board specific values (where the DRA7 EVM surely differs from our setup)?
I hope that helps :)
Can you please try maxing out .sdram_tim3 T_RFC value from 0x027f8be8 to 0x027f8ff8, see commit 2b143578a07afe0e50567f8327f4f62e0703cb20.
Regards,
Tony