The RAM datasheet states tXS must be tRFC + 10ns, and 10ns is 6 cycles in our case.
Signed-off-by: Grazvydas Ignotas notasas@gmail.com --- board/goldelico/letux-cortex15/lc15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c index a618ab4095..4ac5ef8d0e 100644 --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -52,7 +52,7 @@ const struct omap_sysinfo sysinfo = { /* Register sdram_tim2 = EMIF_SDRAM_TIMMING_2 (0x4C000020) */ #define T_XP 4 /* from power-down exit to any command other than a read command */ #define T_ODT 0 /* from ODT enable to write data driven for DDR3. Must be equal to tAONPD */ -#define T_XSNR 144 /* from Self-Refresh exit to any command other than a Read command. For DDR3, the value of tXS must be programmed. */ +#define T_XSNR T_RFC+6 /* from Self-Refresh exit to any command other than a Read command. For DDR3, the value of tXS must be programmed. */ #define T_XSRD 512 /* from Self-Refresh exit to a Read command. For DDR3, the value of tXSDLL must be programmed. */ #define T_RTP 4 /* for the last read command to a Precharge command */ #define T_CKE 3 /* between CKE pin changes */