Hi,
Am 09.11.2016 um 09:43 schrieb Michael Mrozek EvilDragon@openpandora.org:
That's something to check them. As far as I know, Nikolaus thoroughly rechecked all traces that have to do with the power supply on the CPU board and made sure they follow exactly TIs specs earlier this year, because my first idea also were power supply issues.
Well, the specs from TI are everything except "exact". So following them exactly is not possible...
But it might be a good idea to recheck them, in case something has been overlooked.
Indeed.
AFAIK Nikolaus added even more capacitors for this CPU Board revision, but I think they were only for VSYS, not between the PALMAS and OMAP5.
I've asked Nikolaus a couple of days ago to make a package of the current schematics, etc., as the one I have do not reflect all the changes made since the last prototype run (AFAIK).
Yes, I am in the middle of making them drawn a little nicer so that they are easier to read.
Hopefully, he'll find the time soon and can post the schematics here at the mailing list so we can all check and compare it with TIs recommendations.
On November 9, 2016 5:33:49 AM GMT+01:00, Matthijs van Duin matthijsvanduin@gmail.com wrote: On 9 November 2016 at 01:33, Michael Mrozek EvilDragon@openpandora.org wrote: Hm. VDD_MPU is being handled by the PALMAS automatically, as far as I know. It measures the voltage directly at the OMAP5 and adjusts it, so that should be fine.
It's not that simple.
The remote sensing of VDD_MPU allows palmas to compensate mean voltage drop, but it is not going to deal with transients. Even if it could measure and compensate fast enough (it can't), the loop inductance of the power distribution net would probably prevent it from succeeding. (Such an aggressive control loop would also be prone to instability.)
Indeed.
Dealing with transients is still the job of decoupling caps as usual. TI gives quite a bit of guidance on the power distribution nets in general (sections 7.2.1-7.2.4, 7.3 of swps051k)
I didn't find that one but swps050i.
and decoupling caps in particular (e.g. section 7.3.2-7.3.4).
Yes, it is guidance but it is not very helpful in detail. Quite a lot of sentences are "should be" or "as good as possible" or "example". Or "calculate with your design tools". Unfortunately we do not have the big budget we would need to have such tools (e.g. calculate resistance or inductance from PCB layout data).
And we have quite strong space constraints so that not everything can be copied from the EVM (e.g. placing decoupling capacitors on the backside under the OMAP5) or guide lines (there isn't much space for adding more VIAs or moving traces to optimal positions).
So it contains a lot of experience and is a big compromise - but certainly not an optimal one.
I have picked up some unpopulated CPU PCBs this morning and I can try to measure resistances. If they are in the mOhm range (which is to be expected) the precision might not be good.
BR, Nikolaus