Hi,
* Matthijs van Duin matthijsvanduin@gmail.com [160714 18:44]:
Section 4.3.2 of the omap5432 datasheet warns:
The programmable divider for the asynchronous bridge to Audio Back-end (ABE) must be set to:
- MPU_GCLK / 16 when MPU_GCLK clock is running at OPP_HIGH_MPU.
- MPU_GCLK / 8 when MPU_GCLK clock is running at OPP_NOM_MPU.
The programmable divider for the asynchronous bridge to L3 must be set to:
- MPU_GCLK / 8 when MPU_GCLK clock is running at OPP_HIGH_MPU.
- MPU_GCLK / 4 when MPU_GCLK clock is running at OPP_NOM_MPU.
This however does not seem to be happening (tested on 4.7-rc7-letux):
root@omap5:~# cpufreq-set -r -g performance root@omap5:~# omapconf show prcm mpu | grep Rat | Source Clock Rate | 1500.000MHz | | MPU-ABE SS Bridge Ratio | 8 | | MPU-L3MAIN Interc. Bridge Ratio | 4 |
(These settings are in CM_MPU_MPU_CLKCTRL.)
Tero, do you have a fix in mind for this one?
Regards,
Tony