At 08:40 +0200 on Wednesday 2017-09-13, Matthijs van Duin wrote:
We're running the memory bus at 532 MHz, i.e. tCK = 1.88 ns.
At 06:03 +0200 on Monday 2017-09-18, Matthijs van Duin wrote:
DDR3-1066 only has E (CL=6), F (CL=7), and G (CL=8) as JEDEC-specified bins.
The timings are often also specified as 6-6-6 / 7-7-7 / 8-8-8, which refer to CL, nRCD and nRP.
At 06:03 +0200 on Monday 2017-09-18, Matthijs van Duin wrote:
For our memory that's the DDR3-1066F bin, which means it supports 7-7-7 timings (which we're using).
Does the memory bus clock need to run so fast, so close to the maximum for the bin?
With CL = 7 the range is (400, 533 1/3] MHz according to the K4B8G1646D datasheet. 532 MHz seems very close to the top edge.
What happens if you back it off 5% from the bin edge and run the clock at 507 MHz or so?
Or, alternatively, kick the clock up to around 561 MHz (if the board / processor will support that) and use the next bin (533 1/3, 666 2/3] MHz with CL = 9? (Although, according to Matthijs's post, that's not JEDEC standardised.)
N.