12 Mar
2017
12 Mar
'17
3:18 p.m.
On Tue, Mar 07, 2017 at 11:19:53AM +0200, Tero Kristo wrote:
On 06/03/17 19:03, Tony Lindgren wrote:
Yup this is similar to what I recall seeing where the clocks don't always lock on reboot. Adding Tero to Cc if he has a fix in mind for this one.
Haven't faced this issue myself, but ABE is notorious for this kind of issues I recall, due to custom clocking setup for that specific DPLL. Are you tweaking the source of that DPLL?
I don't think we are, not on purpose anyway :)
I can give omap5uevm a shot at some point and see what happens.
I'd offer to try it on my pyra prototype, but I'm still trying to coax it around ddr3 hw leveling failures. Apparently having 6 out of 8 bytelanes working is not enough ;-)
Matthijs