On Sa, 2018-10-13 at 02:31 +0300, Grazvydas Ignotas wrote:
Hi,
Well, hardware- or softwarewise broken?
Probably hardware, there is very little software control for how it does it's thing (see below).
Hm, I wonder what though. The simulation is successful with the correct IBIS files... I'll ask the experts at Memphis again, they know the RAM and might have some clues.
I'll also test how much power consumption differs with Self-Refresh off or on as well.
If I understood correctly, then Self-Refresh is being entered and exited by the kernel. So both the call and the procedure is being controlled by software.
Not on OMAP5's EMIF, here it's all done by EMIF hardware. You can only control the on/off switch for the feature, time how long it has to idle (no RAM access by anything) before it starts the procedure and some limited timing parameters.
Okay, then it probably just follows JEDEC standard which should just work.
But our chip also supports the (optional) feature "Auto Self- Refresh".
How do you know that? It's not mentioned in feature list of our RAM's datasheet.
Well, it says on page 36 of the datasheet: " Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature"
It's just a footnote though, no further mentioning, so it's either a leftover from a different chip or they didn't want to mention it anywhere else. You never know with datasheets...
It's the same with our 2GB IM-Memory. They mention how to enable ASR, but that's it.
If Auto Self-Refresh does the same as Self-Refresh (but it's being handled by the RAM itself), maybe that woukd work instead?
Yes there is a bit for that in OMAP5, might try it later.
Thanks - if that works, it would be great.