Am Wed, 9 Nov 2016 13:41:24 +0100 hat "H. Nikolaus Schaller" hns@goldelico.com geschrieben:
Hi,
That's something to check them. As far as I know, Nikolaus thoroughly rechecked all traces that have to do with the power supply on the CPU board and made sure they follow exactly TIs specs earlier this year, because my first idea also were power supply issues.
Well, the specs from TI are everything except "exact". So following them exactly is not possible...
Hm, in the document Matthijs mentioned, I often fine "must be", etc.
I've asked Nikolaus a couple of days ago to make a package of the current schematics, etc., as the one I have do not reflect all the changes made since the last prototype run (AFAIK).
Yes, I am in the middle of making them drawn a little nicer so that they are easier to read.
Great, thanks!
The remote sensing of VDD_MPU allows palmas to compensate mean voltage drop, but it is not going to deal with transients. Even if it could measure and compensate fast enough (it can't), the loop inductance of the power distribution net would probably prevent it from succeeding. (Such an aggressive control loop would also be prone to instability.)
Indeed.
So that's probably where we need to take a closer look at.
Dealing with transients is still the job of decoupling caps as usual. TI gives quite a bit of guidance on the power distribution nets in general (sections 7.2.1-7.2.4, 7.3 of swps051k)
I didn't find that one but swps050i.
A quick google showed up this one: http://software-dl.ti.com/secure/techdocs/swps051k/swps051k?__gda__=14795634...
You just need to login with your TI account and tell them you don't want to nuclear bomb Trump.
and decoupling caps in particular (e.g. section 7.3.2-7.3.4).
Yes, it is guidance but it is not very helpful in detail. Quite a lot of sentences are "should be" or "as good as possible" or "example". Or "calculate with your design tools". Unfortunately we do not have the big budget we would need to have such tools (e.g. calculate resistance or inductance from PCB layout data).
Not sure if there's a difference, but swps051k quite often has "must" in their text, not should be or similar.
And we have quite strong space constraints so that not everything can be copied from the EVM (e.g. placing decoupling capacitors on the backside under the OMAP5) or guide lines (there isn't much space for adding more VIAs or moving traces to optimal positions).
The backside is completely unpopulated right now, but we have 0,5mm space between it and the case. Should be enough for capacitors, so why, for example, couldn't we put decoupling capacitors there? (This is just an example though, because according to the Datasheet:
"2. Place Dcaps on “same-side” as component within their power plane outline to minimize “decoupling loop inductance”. Target distance to power pin should be less than ~500mils depending upon PCB layout characteristics (plane's layer assignment and solid nature). Use PI modeling CAD tool to verify minimum inductance for top vs bottom-side placement."
So it's better to have the DCaps on the same side of the OMAP5 anyways.
Except for:
"Place Dcaps on “opposite-side” as component within their power plane outline if “same-side” is not feasible or if distance to power pin is greater than ~500mils for top-side location."
How many mils are we away from the power pin?
Looking at 7.2.2 of the document, it also seems VERY important to have multiple vias (not one for multiple capacitors), etc.
If I understand correctly, what we need to check for are the IR drop and capacitance-inductance loop requirements... I have no idea how these can be checked though (I'm not really experienced here). Is that something you simulate from the PCB design files?
And something we should also check: "Use minimum 10mil trace width for all voltage and gnd planes connections (i.e. Dcap pads, component power pins, etc.)."
"Use a “Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not exceed 2:1 ratio for small number of vias within restricted PCB areas (i.e. underneath BGA components)."
So it contains a lot of experience and is a big compromise - but certainly not an optimal one.
I also think we're not that far off! Maybe just a change in the decoupling capacitors could fix things...
"7.3.2 Voltage Decoupling" of the file is interesting here.
The recommend various decoupling capacitors, so we might have some ways to play around here. And capacitors can be changed without changing the board design.
"For power IC which can support more than 10uF close to processor, a bulk capacitor of at least 22uF is strongly recommended for VDD_MPU power domains."
Do we have that? :)
I have picked up some unpopulated CPU PCBs this morning and I can try to measure resistances. If they are in the mOhm range (which is to be expected) the precision might not be good.
Okay!