This adds the Vivante GC320 to the device tree and to the hwmod data.
Original-by: Robert Nelson robertcnelson@gmail.com Signed-off-by: David Shah dave@ds0.me --- arch/arm/boot/dts/omap5-board-common.dtsi | 4 +++ arch/arm/boot/dts/omap5.dtsi | 10 +++++++ arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 32 ++++++++++++++++++++++ 3 files changed, 46 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 62d8c3eb4547..efee0e4adfa3 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -785,3 +785,7 @@ hdmi_out: endpoint { }; }; }; + +&bb2d { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 54af46254afc..bc5915689f8b 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -223,6 +223,16 @@ dmm@4e000000 { ti,hwmods = "dmm"; };
+ bb2d: bb2d@59000000 { + compatible = "vivante,gc"; + reg = <0x59000000 0x0700>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, // bus: DSS_L3_GICLK + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 13>; // core: BB2D_GFCLK + clock-names = "bus", "core"; + ti,hwmods = "bb2d"; + }; + emif1: emif@4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index ad398f6bc011..19eee76deddf 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -768,6 +768,37 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = { .user = OCP_USER_MPU | OCP_USER_SDMA, };
+/* 'bb2d' class + * GC320 2D GPU + */ + +static struct omap_hwmod_class omap54xx_bb2d_hwmod_class = { + .name = "bb2d", +}; + +/* bb2d */ +static struct omap_hwmod omap54xx_bb2d_hwmod = { + .name = "bb2d", + .class = &omap54xx_bb2d_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "dpll_core_h24x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* l3_main_1 -> bb2d */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__bb2d = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_bb2d_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* * Interfaces */ @@ -1029,6 +1060,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l3_main_2__l4_per, &omap54xx_l3_main_1__l4_wkup, &omap54xx_mpu__mpu_private, + &omap54xx_l3_main_1__bb2d, &omap54xx_l4_wkup__counter_32k, &omap54xx_l3_main_2__dss, &omap54xx_l3_main_2__dss_dispc,