* Mr C Camacho chriscamacho@virginmedia.com [181017 15:35]:
On Wed, 17 Oct 2018 10:14:33 +0200 "H. Nikolaus Schaller" hns@goldelico.com wrote:
My theory: EMIF assumes that each chip has separate clock cka and ckb. Now EMIF can turn off cka to save energy. It does not know that cka does also serve the second die because it assumes that it is connected to ckb. So it keeps ckb running but the chip has no clock.
Yeah this seems like the best explanation so far.
Note that in am57xx TRM things seem different as in "Figure 17-46. EMIF DDR2/DDR3 Configuration Without ECC" there's just CK ddri_ck listed, so not sure what has changed.
But without information I can't prove or disprove this or find out what consequences this has.
Is there anyway to boot with all the lower 2GB reserved (for nothing) forcing only the upper 2GB to be used, it might possibly give a clue as to whats going on ?
Yeah this is easy to do, see the test patch below. It maps 2GB from emif2 with no interleaving. With interleaving the map_2 value would be 0x80700300 which is the default. That's the TRM register for "Table 15-49. DMM_LISA_MAP_i".
This works just fine for self-refresh. But if any configuration is added for kernel for emif1 also, self-refresh will hang the system it seems.
No idea what the connection is between emif1 and emif2 related to the self-refresh hang without interleaving copnfigured though.
Regards,
Tony
8< --------------------- diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -103,6 +103,20 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_ddr3_532_mhz_2cs_es2; }
+const struct dmm_lisa_map_regs lisa_map_cm_pyra = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80700200, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1, +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &lisa_map_cm_pyra; +} + +#if 0 void dram_init_banksize(void) { /* make U-Boot pass the same as bootarg "mem=2032M@0x80000000 mem=2048M@0x200000000" would do */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; // == 0x80000000 @@ -117,6 +131,7 @@ void dram_init_banksize(void) gd->ram_size = gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size; } #endif +#endif
/* * Board Revision Detection