15 Apr
2020
15 Apr
'20
10:12 a.m.
Hi,
On Wed, Apr 15, 2020 at 10:35:08AM +0200, H. Nikolaus Schaller wrote:
The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, Allwinner A83 and others.
With this binding, we describe how the SGX processor is interfaced to the SoC (registers, interrupt etc.).
In most cases, Clock, Reset and power management is handled by a parent node or elsewhere (e.g. code in the driver).
Wouldn't the "code in the driver" still require the clock / reset / power domain to be set in the DT?
Maxime