Re: [PATCH 1/4] emif: make omap5_ddr3_init more similar to dra7_ddr3_init

* Tony Lindgren tony@atomide.com [181016 18:04]:

I wonder if some of the ddr3 control signals could be crossed, or if some control signals need to be left out for emif2?

So here I'm thinking TRM "Figure 15-46. EMIF DDR3 Generic Configuration" that shows the lines that should be different for each die:

CK NCK ODT CKE NCS

So each emif has two chips with each chip having two dies. To me it seems Figure 15-46 matches how it should be?

So the signals listed above should be selectively connected for each chip in the emif and not to both chips on the emif?

Regards,

Tony