Should be much easier to compare against the datasheet. No actual register changes introduced by this change.
Partially based on IGEPv5 u-boot: https://git.isee.biz/arm-boot/u-boot-arm/blob/u-boot-2014.01.y-omap5/board/i...
Signed-off-by: Grazvydas Ignotas notasas@gmail.com --- board/goldelico/letux-cortex15/lc15.c | 43 +++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c index fdf4a67198..a618ab4095 100644 --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -36,15 +36,52 @@ const struct omap_sysinfo sysinfo = { * NOTE: please run a kernel with LPAE enabled to make use of the 4GB RAM! */
+/* Register sdram_tim1 = EMIF_SDRAM_TIMMING_1 (0x4C000018) */ +#define T_RTW 7 /* between Read to Write data phases.*/ +#define T_RP 7 /* Precharge to Activate or Refresh. */ +#define T_RCD 7 /* Activate to Read or Write. */ +#define T_WR 8 /* last Write transfer to Precharge. */ +#define T_RAS 20 /* Activate to Precharge. >= T_RCD value */ +#define T_RC 27 /* Activate to Activate. */ +#define T_RRD 7 /* Activate to Activate for a different bank. For an 8-bank, ((tFAW / (4 × tCK)) - 1) */ +#define T_WTR 4 /* last Write to Read. */ +#define T_SDRAM_TIM1 \ + ((T_RTW-1) << 29) | ((T_RP-1) << 25) | ((T_RCD-1) << 21) | ((T_WR-1) << 17) \ + | ((T_RAS-1) << 12) | ((T_RC-1) << 6) | ((T_RRD-1) << 3) | ((T_WTR-1)) + +/* Register sdram_tim2 = EMIF_SDRAM_TIMMING_2 (0x4C000020) */ +#define T_XP 4 /* from power-down exit to any command other than a read command */ +#define T_ODT 0 /* from ODT enable to write data driven for DDR3. Must be equal to tAONPD */ +#define T_XSNR 144 /* from Self-Refresh exit to any command other than a Read command. For DDR3, the value of tXS must be programmed. */ +#define T_XSRD 512 /* from Self-Refresh exit to a Read command. For DDR3, the value of tXSDLL must be programmed. */ +#define T_RTP 4 /* for the last read command to a Precharge command */ +#define T_CKE 3 /* between CKE pin changes */ +#define T_SDRAM_TIM2 \ + ((T_XP-1) << 28) | (T_ODT << 25) | ((T_XSNR-1) << 16) | ((T_XSRD-1) << 6) \ + | ((T_RTP-1) << 3) | (T_CKE-1) + +/* Register sdram_tim3 = EMIF_SDRAM_TIMMING_3 (0x4C000028) */ +#define T_PDLL_UL 0 /* cycles for PHY DLL to unlock. A value of N will be equal to N x 128 clocks */ +#define T_CSTA 3 /* between write-to-write or read-to-read data phases to different chip selects. */ +#define T_CKESR 4 /* cycles for which SDRAM must remain in Self Refresh */ +#define T_ZQ_ZQCS 64 /* cycles for a ZQCS command. */ +#define T_TDQSCKMAX 1 /* clock that satisfies tDQSCKmax for LPDDR2. */ +#define T_RFC 191 /* DDR clock cycles from Refresh or Load Mode to Refresh or Activate.*/ +#define T_RAS_MAX 8 /* Maximum number of REFRESH_RATE intervals from Activate to Precharge command */ +#define T_SDRAM_TIM3 \ + (T_PDLL_UL << 28) | ((T_CSTA-1) << 24) | ((T_CKESR-1) << 21) \ + | ((T_ZQ_ZQCS-1) << 15) | ((T_TDQSCKMAX-1) << 13) | ((T_RFC-1) << 4) | T_RAS_MAX + + const struct emif_regs emif_regs_ddr3_532_mhz_2cs_es2 = { .sdram_config_init = 0x61851B3A, .sdram_config = 0x61851B3A, .sdram_config2 = 0x0, .ref_ctrl = 0x000040F1, .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, - .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F8BE8, + .sdram_tim1 = T_SDRAM_TIM1, + .sdram_tim2 = T_SDRAM_TIM2, + .sdram_tim3 = T_SDRAM_TIM3, .read_idle_ctrl = 0x00050000, .zq_config = 0xD007190B, .temp_alert_config = 0x00000000,