* Michael Mrozek EvilDragon@openpandora.org [180920 11:13]:
On Do, 2018-09-20 at 09:29 -0700, Tony Lindgren wrote:
Also, simply comparing the values to the datasheet might help as well.
Yes please do check again :)
Just tried doing that, I have a few questions though:
- Is there an EMIF-Tool for the OMAP5 as well? I only found the EMIF
RegisterConfig Rev 2.0.1 (which is for the DRA7 and similar. The one I used is this one: http://www.ti.com/lit/an/sprac36b/sprac36b.zip
Not that I know. Note that dra7 is different for at least levelling, so some registers might be different too. There's a tool for am437x that might be similar to omap5, but I don't think it supports 532MHz rate.
- Table 1 (Step1-SystemDetails) requires system details like ODT,
Output Driver Impedance, etc. Aren't these dependant on our board layout? How can we get these? It says "** NOTE: IBIS models should be used for signal integrity analysis. I/O settings programmed should match simulation settings."... so can we get these values from Juliano?
- Does the OMAP5 support Hardware Levelling and have we enabled that?
Otherwise, we need the trace lengths (according to Step2-BoardDetails).
Yes that's done AFAIK on boot. That too might have issues remaining.
- On Step3-DDRTimings, most timings are already exactly like they say
in our datasheet. Some values are "minimum" or "maximum". Are these values we can play around with to give the RAM a bit more safety?
I think they are the accepted JEDEC range.
5.As mentioned, those specs are exactly the same as in our datasheet. Howeve, I noticed that tfRAW has the value 50 pre-setup in the tool (which is for 2KB page size) whereas the value tRRD has the value 7.5 pre-setup in the tool (which is for 1KB page size). Is that a mismatch or doesn't that matter?
Hmm that might be worth testing.
- Some values the tool spits out are different than what we have in U-
Boot. Some examples: .sdram_config and .sdram_config_init: 0x61851BB2 in the EMIF tool, 0x61851B3A in U-Boot.
For sdram_config_init, it needs to have 2 chip selects per ddr so pyra-4g has 4 chip selects total. So ROWSIZE we seem to have wrong for 4Gb, it should be 16 not 15, but I think that's cosmetic.
.sdram_tim1 is 0xCCCF36B5 according to the EMIF Tool, but we use 0xCCCF36B3 (so a bit lower).
This value seems to make no difference, it works the same way and could be used.
.emif_ddr_phy_ctlr_1_init is 0x0024400B in the EMIF Tool, but we are using 0x0030400A.
And emif_ddr_phy_ctlr_1_init needs to be configured in addition to emif_ddr_phy_ctlr_1 with PHY_INVERT_CLKOUT cleared for emif_ddr_phy_ctlr_1_init. So this would translate to values:
.emif_ddr_phy_ctlr_1_init = 0x0020400B, .emif_ddr_phy_ctlr_1 = 0x0024400B,
They too work just the same and could be used.
.emif_rd_wr_exec_thresh is 0x00000305 in the EMIF Tool, we're using 0x40000305
This emif_rd_wr_exec_thresh is missing LL_BUBBLE_ENABLE, so no change to what we have.
.zq_config results in 0x5007190B and we're using 0xD007190B,
And zq_config is missing ZQ_CS1EN, so we have the same value after that already.
So yeah, there ARE some differences - though I have no idea what these values mean. Do they have something to do with those board specific values (where the DRA7 EVM surely differs from our setup)?
I think we need to check any idle dll affecting values again considering disabling the internal dll hack prevents the idle hang based on brief testing..
Regards,
Tony