Based on igepv5 u-boot commit 4521f304a913 ("IGEPv5: Modify lisa_regs structure, added ma_hm_interleave variable") by Manel Caro mcaro@iseebcn.com, we need to configure interleaving for 4GB DDR3 to work properly.
With out this patch u-boot somehow has hard time booting reliably even with smps6 set to 1.50V and termination set to 0.
Note that with interleaving the memory addresses are different if passed from kernel command line. Typically those can be left out as u-boot will pass them. --- arch/arm/cpu/armv7/omap-common/emif-common.c | 5 +++++ arch/arm/include/asm/emif.h | 1 + board/goldelico/letux-cortex15/lc15.c | 18 ++++++++++++++++-- 3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1339,6 +1339,11 @@ void dmm_init(u32 base) &hw_lisa_map_regs->dmm_lisa_map_0);
setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); + + /* MA_PRIORITY[8] HIMEM_INTERLEAVE_UN bit to 0x1 */ + if (lisa_map_regs->is_ma_hm_interleave) + __raw_writel(__raw_readl(MA_PRIORITY) | + (1 << 8) , MA_PRIORITY); }
/* diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -756,6 +756,7 @@ struct dmm_lisa_map_regs { u32 dmm_lisa_map_2; u32 dmm_lisa_map_3; u8 is_ma_present; + u8 is_ma_hm_interleave; };
#define CS0 0 diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -69,10 +69,10 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) }
void dram_init_banksize(void) -{ /* make U-Boot pass the same as bootarg "mem=2032M@0x80000000 mem=2048M@0x200000000" would do */ +{ /* make U-Boot pass the same as bootarg "mem=2032M@0x80000000 mem=2048M@0x300000000" would do */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; // == 0x80000000 gd->bd->bi_dram[0].size = 2032*(1024UL*1024); // first 2GB - gd->bd->bi_dram[1].start = 0x200000000UL; + gd->bd->bi_dram[1].start = 0x300000000UL; gd->bd->bi_dram[1].size = 2048*(1024UL*1024); // second 2GB #if 0 // get back "stolen" memory gd->bd->bi_dram[1].start = 0x2FF000000UL; @@ -81,6 +81,20 @@ void dram_init_banksize(void) /* report 4 GB during boot */ gd->ram_size = gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size; } + +const struct dmm_lisa_map_regs lisa_map_pyra_4g = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x807C0300, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1, + .is_ma_hm_interleave = 0x1, +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &lisa_map_pyra_4g; +} #endif
/*