Am Wed, 6 Sep 2017 22:05:38 -0700 hat Tony Lindgren tony@atomide.com geschrieben:
Hi,
nice! Is that with 1,35V as well?
The interesting thing is about the cool down... I wonder if that works better when we have the cooling applied. I'll build another unit with cooling and a 4GB board for testing.
I was wondering about the weird non-sensical 0xffff ref_ctrl and was thinking maybe we have multiple clocks going? And by setting ref_ctrl to 0xffff we stop their interaction for most part and this allowed me to boot kernel and run memtester..
Anyways, setting bit 20 to disable DDR3 internal DLL allowed me to remove the weird non-sensical 0xffff value for ref_ctrl. And further testing showed that this also allows removing the rest of the hacks as well and I can run two instances of memtester 1900M with Matthij's timings!
Note that the board needs to be let cool down before booting, otherwise you can get the "dq test failed" errors in u-boot.
board/goldelico/letux-cortex15/lc15.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -37,8 +37,8 @@ const struct omap_sysinfo sysinfo = { */
const struct emif_regs emif_regs_ddr3_532_mhz_2cs_es2 = {
- .sdram_config_init = 0x61851B3A,
- .sdram_config = 0x61851B3A,
- .sdram_config_init = 0x61951B3A,
- .sdram_config = 0x61951B3A, .sdram_config2 = 0x0, .ref_ctrl = 0x00001035, .sdram_tim1 = 0xCCCF36B3,