Hi Tony,
Am 17.10.2018 um 01:03 schrieb Tony Lindgren tony@atomide.com:
- H. Nikolaus Schaller hns@goldelico.com [181016 19:25]:
Hi Tony,
Am 16.10.2018 um 20:19 schrieb Tony Lindgren tony@atomide.com:
- Tony Lindgren tony@atomide.com [181016 18:04]:
I wonder if some of the ddr3 control signals could be crossed, or if some control signals need to be left out for emif2?
So here I'm thinking TRM "Figure 15-46. EMIF DDR3 Generic Configuration"
in my TRM (Version Y) there is Figure 16-48. EMIF DDR3 Generic Configuration.
that shows the lines that should be different for each die:
CK NCK ODT CKE NCS
So each emif has two chips with each chip having two dies. To me it seems Figure 15-46 matches how it should be?
Yes.
So the signals listed above should be selectively connected for each chip in the emif and not to both chips on the emif?
I have checked the schematics and there are for each dual-die chip:
CK (common to both dies) NCK (common to both dies) ODT0, ODT1 (individual for each die) CKE0, CKE1 (individual for each die) NCS0, NCS1 (individual for each die)
Which means both dies share the same clock but have the other controls separately.
EMIF provides CKA, NCKA, CKB and NCKB. The first two are connected to CK, NCK and the other two are not connected. We can't connect (N)CKB anywhere because the dual-die chips have no separate clock inputs...
Well looking at the Pyra schematics to me it seems that for example on emif1 cke0 and cke1 are both connected to U3401 and U3402. To me it seems U3401 should only have cke0 and U3402 should have only cke1 (or the other way around) just as in "EMIF DDR3 Generic Configuration". And the same for the other used lines, and for emif2.
Are you sure with oyur idea?
U3401 is for 16 bits and U3402 for the other 16 bits of the 32 bit EMIF channel.
Both, U3401 and U3402 have two dies inside where one responds to ODT/CKE/NCS0 and the other to ODT/CKE/NCS1. So U3401 combines what is shown as "Die 1" and "Die 2" in the figure and U3402 combines "Die 3" and "Die 4". So ODT/CKE/NCS0 and ODT/CKE/NCS1 must be connected to a single U340x.
Cutting either would IMHO make half of the memory capacity unaccessible.
This would mean the EMIF must be programmed in a way that takes care of this shared clocks...
Hm. Could it be that the configuration assumes clka and clkb being enabled/disabled separately for self-refresh. And then for example clka is stopped? Which also stops the clock of cke1 die which isn't expected by the EMIF?
I'm guessing that taking a 1mm drill bit and drilling out CKE1 ball from U3401 and CKE0 U3402 ball slightly sideways might fix it if there is enough room around the ddr3 chips and somebody wants to try :)
Probably the NCS0 and 1 would need to be modified too.. And for all the four chips in a similar way.
Regards,
Tony
BR, Nikolaus