On Mo, 2017-09-18 at 21:11 +0200, Matthijs van Duin wrote:
Well, sure, it wouldn't be the solution, but might be interesting to see if it works.
I still find it weird though that it probably works with DLL off but full speed :O
What happens if you back it off 5% from the bin edge and run the clock at 507 MHz or so?
The memory is binned for CL=7 @ 533 MHz, which means the manufacturer guarantees those timings. I'm also fairly sure that CL is only relevant for timing closure internal to the memory, hence increasing it won't fix issues with the interfacing between memory and omap.
Of course lowering the clock frequency could nevertheless be beneficial since gives all nets (both signal and power) more time to stabilize again after a transition. Doing so however would require lowering the frequency of the core PLL and thereby all clocks that derive from it (which include all interconnects and the GPU), which would be annoying from a performance point of view.
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