On 7 March 2017 at 04:24, Matthijs van Duin matthijsvanduin@gmail.com wrote:
My impression is that ddr3 leveling is failing. EMIF has a history of buggy hardware leveling, and incremental (as opposed to full) leveling is still marked as not-supported for omap5 and dra7. I'm also seeing lots of error flags set in the phy after leveling, though curiously that's also the case when it does boot, so maybe the flags are just garbage. I'll see if I can print more informative debug info about what's going on during EMIF initialization.
Well, this has been informative, although I'm not sure yet what conclusions to draw...
In case anyone else wants a vomit of ddr3 timings across their console at boot, I've pushed my verbose emif debugging patches to github: https://github.com/mvduin/u-boot
My repo is rather a mess of unrelated patches, but the three emif patches are at the top and can probably be cherry-picked cleanly.
Here's an apparently-successful power-up into u-boot:
do_sdram_init() 4c000000
omap5_ddr3_leveling(0x4c000000) cmd phy dlls: ok f6 ok f5 data phy dlls: ok f7 ok f4 ok fc ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 7f 40 7f 3c 41 43 3a 3b fifo we ratios: 69 7d 72 76 69 7d 73 74 write data ratios: 10a 6e 10a 7a 75 6d 6f 78 write dqs ratios: ea 4e ea 5a 55 4d 4f 58 fifo misalignment: yes yes yes yes fifo rst errors: 2 5 3 4 cmd phy dlls: ok f6 ok f5 data phy dlls: ok f8 ok f3 ok fc ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 7e 41 7e 3c 41 44 3a 3b fifo we ratios: 68 7c 71 75 68 7c 72 73 write data ratios: 103 6c 100 78 74 6b 6e 77 write dqs ratios: e3 4c e0 58 54 4b 4e 57 leveling errors: -w- --- -w- -w- fifo rst errors: 0 2 0 2 <<do_sdram_init() 4c000000
do_sdram_init() 4d000000
omap5_ddr3_leveling(0x4d000000) cmd phy dlls: ok f9 ok fb data phy dlls: ok f6 ok fb ok fc ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3a 3a 37 46 3d 39 39 45 fifo we ratios: 70 79 7a 74 75 78 7f 72 write data ratios: 78 72 7a 78 77 70 7b 76 write dqs ratios: 58 52 5a 58 57 50 5b 56 fifo misalignment: yes yes yes yes fifo rst errors: 2 3 5 2 cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fc ok fb ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3b 3b 36 46 3e 38 39 45 fifo we ratios: 6f 78 79 74 74 77 7e 71 write data ratios: 76 70 79 78 75 6f 79 76 write dqs ratios: 56 50 59 58 55 4f 59 56 leveling errors: -w- rw- --- -w- fifo misalignment: - - - yes fifo rst errors: 1 2 1 2 <<do_sdram_init() 4d000000 get_ram_size() successful
This again is "success":
do_sdram_init() 4c000000
omap5_ddr3_leveling(0x4c000000) cmd phy dlls: ok f7 ok f6 data phy dlls: ok f9 ok f4 ok fd ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 7f 41 7f 3b 40 44 3a 3b fifo we ratios: 6a 7d 74 77 6a 7e 74 76 write data ratios: 10a 6e 10a 79 75 6e 6f 78 write dqs ratios: ea 4e ea 59 55 4e 4f 58 fifo misalignment: yes yes yes yes fifo rst errors: 2 5 4 3 cmd phy dlls: ok f7 ok f6 data phy dlls: ok f9 ok f4 ok fc ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 7e 41 7e 3b 41 44 3a 3b fifo we ratios: 69 7c 73 76 69 7d 73 75 write data ratios: 103 6c 100 78 73 6b 6d 76 write dqs ratios: e3 4c e0 58 53 4b 4d 56 leveling errors: --- -w- --- --- fifo rst errors: 1 2 0 2 <<do_sdram_init() 4c000000
do_sdram_init() 4d000000
omap5_ddr3_leveling(0x4d000000) cmd phy dlls: ok f8 ok fc data phy dlls: ok f7 ok fb ok fb ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3b 3c 37 46 3d 39 39 45 fifo we ratios: 70 79 7b 76 75 76 7f 71 write data ratios: 78 71 7a 78 76 70 7c 77 write dqs ratios: 58 51 5a 58 56 50 5c 57 fifo misalignment: yes yes yes yes fifo rst errors: 2 4 5 2 cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fb ok fc ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3c 3c 37 46 3e 38 39 45 fifo we ratios: 6f 78 7a 75 74 75 7e 72 write data ratios: 76 6f 78 75 74 6f 79 75 write dqs ratios: 56 4f 58 55 54 4f 59 55 leveling errors: --- rw- --- --g fifo misalignment: - - - yes fifo rst errors: 1 1 1 2 <<do_sdram_init() 4d000000 get_ram_size() successful
Even ignoring the leveling errors (which could be bogus), the read fifo errors seem very serious to me. Nevertheless u-boot seemed to work fine, and I've even run a memory test (mtest $loadaddr $fdtaddr) which also seemed to confirm that there were no problems with memory.
I also have trouble believing the write leveling values for EMIF1 rank 0 bytes 0 and 2 could possibly be right considering how much larger they are than all others, especially since rank 0+1 bytes 0+1 are in a single package and ditto rank 0+1 bytes 2+3. It's possible though that there's enough margin that it can get away with those settings, but in that case it's quite an accomplishment that it also manages to pick non-working timings :P
Here for example is a failed boot:
do_sdram_init() 4c000000
omap5_ddr3_leveling(0x4c000000) cmd phy dlls: ok f6 ok f5 data phy dlls: ok f8 ok f3 ok fc ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 3e 44 3a 3b 7f 44 3b 3a fifo we ratios: 69 7c 73 75 1b 7c 74 76 write data ratios: 77 6f 70 79 76 6e 70 79 write dqs ratios: 57 4f 50 59 56 4e 50 59 fifo misalignment: yes yes yes yes fifo rst errors: 15 4 2 3 cmd phy dlls: ok f6 ok f5 data phy dlls: ok f7 ok f3 ok fb ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 3e 45 3a 3b 7e 45 3b 3a fifo we ratios: 68 7d 72 74 1a 7b 73 75 write data ratios: 75 6d 6d 78 74 6b 6d 76 write dqs ratios: 55 4d 4d 58 54 4b 4d 56 leveling errors: rw- --- --- --- fifo misalignment: yes yes - - fifo rst errors: 1 2 1 2 <<do_sdram_init() 4c000000
do_sdram_init() 4d000000
omap5_ddr3_leveling(0x4d000000) cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fc ok fc ok f4 phy status 5-7: 0 99990924 924 read dqs ratios: 3c 3a 38 46 3d 38 39 45 fifo we ratios: 71 77 7c 75 73 77 7e 73 write data ratios: 78 71 7c 78 78 70 7b 77 write dqs ratios: 58 51 5c 58 58 50 5b 57 fifo misalignment: yes yes yes yes fifo rst errors: 2 4 5 2 cmd phy dlls: ok f9 ok fb data phy dlls: ok f7 ok fb ok fb ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3c 3b 38 46 3d 39 3a 45 fifo we ratios: 70 76 7b 74 72 76 7d 72 write data ratios: 75 71 7a 76 74 6d 79 75 write dqs ratios: 55 51 5a 56 54 4d 59 55 leveling errors: --- --- -w- --- fifo rst errors: 2 1 2 2 <<do_sdram_init() 4d000000 ### SDRAM: identified: 0 expected: 40000000 ###
This time no problems with write-leveling (other than the phy reporting errors with it) but it completely screwed up the read-leveling of EMIF1 rank 1 lane 0...
As final example, below is the u-boot log showing the "memory" effect of repeated similar failures across power cycling (my patches perform poweroff() when the memory test fails) until it finally succeeds. This time I was testing in 2GB configuration, hence the rank 1 values are nonsense and can be ignored.
This is also the first time I've seen leveling fail entirely, resulting in timeouts.
U-Boot SPL 2016.11-00249-gcb460d33abe8 (Mar 07 2017 - 09:18:21) OMAP5432-GP ES2.0
sdram_init()
in_sdram = 0
do_sdram_init() 4c000000
omap5_ddr3_leveling(0x4c000000) ddr3 write leveling timeout ddr3 read dqs gate training timeout cmd phy dlls: ok f6 ok f6 data phy dlls: ok f8 ok f4 ok fc ok f7 phy status 5-7: 0 99990820 924 read dqs ratios: 7f 40 7f 3b 0 0 0 0 fifo we ratios: 0 7d 0 74 700 700 700 700 write data ratios: 10a 6e 10a 79 36b 307 365 353 write dqs ratios: ea 4e ea 59 34b 2e7 345 333 fifo misalignment: - yes - yes fifo rst errors: 15 1 15 0 cmd phy dlls: ok f6 ok f6 data phy dlls: ok f8 ok f3 ok fb ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 7e 41 7e 3b 0 0 0 0 fifo we ratios: 7ff 7c 7ff 73 700 700 700 700 write data ratios: 106 6c 102 78 36b 307 365 353 write dqs ratios: e6 4c e2 58 34b 2e7 345 333 leveling errors: r-- --- r-- -w- fifo misalignment: yes - yes - fifo rst errors: 0 1 0 1 <<do_sdram_init() 4c000000
do_sdram_init() 4d000000
omap5_ddr3_leveling(0x4d000000) cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fc ok fc ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3d 3b 38 46 0 0 0 0 fifo we ratios: 71 79 7b 75 700 700 700 700 write data ratios: 77 72 7b 78 1b3 3eb 287 d7 write dqs ratios: 57 52 5b 58 193 3cb 267 b7 fifo misalignment: yes yes yes yes fifo rst errors: 2 1 2 2 cmd phy dlls: ok f9 ok fc data phy dlls: ok f6 ok fc ok fc ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3d 3c 38 46 0 0 0 0 fifo we ratios: 70 78 7a 74 700 700 700 700 write data ratios: 75 70 78 76 1b3 3eb 287 d7 write dqs ratios: 55 50 58 56 193 3cb 267 b7 fifo rst errors: 0 1 0 1 <<do_sdram_init() 4d000000 ### SDRAM: identified: 4 expected: 40000000 ###
U-Boot SPL 2016.11-00249-gcb460d33abe8 (Mar 07 2017 - 09:18:21) OMAP5432-GP ES2.0
sdram_init()
in_sdram = 0
do_sdram_init() 4c000000
omap5_ddr3_leveling(0x4c000000) ddr3 write leveling timeout ddr3 read dqs gate training timeout cmd phy dlls: ok f7 ok f6 data phy dlls: ok f8 ok f4 ok fc ok f8 phy status 5-7: c1 99990820 924 read dqs ratios: 7f 42 7f 3c 0 0 0 0 fifo we ratios: 0 7d 0 75 700 700 700 700 write data ratios: 10a 6e 10a 79 38b 307 365 12 write dqs ratios: ea 4e ea 59 36b 2e7 345 3f2 fifo misalignment: - yes - yes fifo rst errors: 15 2 15 1 cmd phy dlls: ok f6 ok f6 data phy dlls: ok f8 ok f4 ok fc ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 7e 42 7e 3d 0 0 0 0 fifo we ratios: 7ff 7e 7ff 75 700 700 700 700 write data ratios: 106 6c 102 79 38b 307 365 12 write dqs ratios: e6 4c e2 59 36b 2e7 345 3f2 leveling errors: r-- --g r-- -w- fifo misalignment: yes yes yes yes fifo rst errors: 0 1 0 0 <<do_sdram_init() 4c000000
do_sdram_init() 4d000000
omap5_ddr3_leveling(0x4d000000) cmd phy dlls: ok f9 ok fb data phy dlls: ok f7 ok fb ok fb ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3b 3b 37 46 0 0 0 0 fifo we ratios: 6f 7b 7b 75 700 700 700 700 write data ratios: 78 71 7c 78 1b3 3eb 292 51 write dqs ratios: 58 51 5c 58 193 3cb 272 31 fifo misalignment: yes yes yes yes fifo rst errors: 1 2 2 2 cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fc ok fc ok f4 phy status 5-7: 0 99990924 924 read dqs ratios: 3b 3b 37 46 0 0 0 0 fifo we ratios: 6e 7a 7a 74 700 700 700 700 write data ratios: 75 70 79 77 1b3 3eb 292 51 write dqs ratios: 55 50 59 57 193 3cb 272 31 leveling errors: --- --- -w- --- fifo rst errors: 1 1 1 1 <<do_sdram_init() 4d000000 ### SDRAM: identified: 4 expected: 40000000 ###
U-Boot SPL 2016.11-00249-gcb460d33abe8 (Mar 07 2017 - 09:18:21) OMAP5432-GP ES2.0
sdram_init()
in_sdram = 0
do_sdram_init() 4c000000
emif_reset_phy(0x4c000000) omap5_ddr3_leveling(0x4c000000) cmd phy dlls: ok f6 ok f6 data phy dlls: ok f7 ok f3 ok fc ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 0 0 0 0 0 0 0 0 fifo we ratios: 700 700 700 700 700 700 700 700 write data ratios: 28e 1bb 2f 117 34b 2e7 345 332 write dqs ratios: 28e 1bb 2f 117 34b 2e7 345 332 cmd phy dlls: ok f7 ok f6 data phy dlls: ok f8 ok f3 ok fc ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 0 0 0 0 0 0 0 0 fifo we ratios: 700 700 700 700 700 700 700 700 write data ratios: 28e 1bb 2f 117 34b 2e7 345 332 write dqs ratios: 28e 1bb 2f 117 34b 2e7 345 332 <<do_sdram_init() 4c000000
do_sdram_init() 4d000000
emif_reset_phy(0x4d000000) omap5_ddr3_leveling(0x4d000000) cmd phy dlls: ok f9 ok fc data phy dlls: ok f6 ok fb ok fc ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 0 0 0 0 0 0 0 0 fifo we ratios: 700 700 700 700 700 700 700 700 write data ratios: e3 39b 276 2f 19b 3cb 262 39 write dqs ratios: e3 39b 276 2f 19b 3cb 262 39 cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fc ok fc ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 0 0 0 0 0 0 0 0 fifo we ratios: 700 700 700 700 700 700 700 700 write data ratios: e3 39b 276 2f 19b 3cb 262 39 write dqs ratios: e3 39b 276 2f 19b 3cb 262 39 <<do_sdram_init() 4d000000 ### SDRAM: identified: 4 expected: 40000000 ###
U-Boot SPL 2016.11-00249-gcb460d33abe8 (Mar 07 2017 - 09:18:21) OMAP5432-GP ES2.0
sdram_init()
in_sdram = 0
do_sdram_init() 4c000000
omap5_ddr3_leveling(0x4c000000) ddr3 write leveling timeout ddr3 read dqs gate training timeout cmd phy dlls: ok f7 ok f6 data phy dlls: ok f8 ok f4 ok fc ok f7 phy status 5-7: 0 99990820 924 read dqs ratios: 7f 41 7f 3c 0 0 0 0 fifo we ratios: 0 7d 0 74 700 700 700 700 write data ratios: 10a 6e 10a 79 26b 30f 365 12 write dqs ratios: ea 4e ea 59 24b 2ef 345 3f2 fifo misalignment: - yes - yes fifo rst errors: 15 2 15 1 cmd phy dlls: ok f6 ok f6 data phy dlls: ok f8 ok f4 ok fc ok f8 phy status 5-7: 0 99990924 924 read dqs ratios: 7e 41 7e 3d 0 0 0 0 fifo we ratios: 7ff 7c 7ff 73 700 700 700 700 write data ratios: 105 6d 103 78 26b 30f 365 12 write dqs ratios: e5 4d e3 58 24b 2ef 345 3f2 leveling errors: r-- -w- r-- -w- fifo misalignment: yes - yes - fifo rst errors: 0 1 0 1 <<do_sdram_init() 4c000000
do_sdram_init() 4d000000
omap5_ddr3_leveling(0x4d000000) cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fb ok fb ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3b 3b 36 46 0 0 0 0 fifo we ratios: 70 7c 7c 77 700 700 700 700 write data ratios: 76 71 7b 77 1b3 2eb 292 51 write dqs ratios: 56 51 5b 57 193 2cb 272 31 fifo misalignment: yes yes yes yes fifo rst errors: 1 3 2 2 cmd phy dlls: ok f8 ok fc data phy dlls: ok f6 ok fb ok fb ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3b 3b 37 46 0 0 0 0 fifo we ratios: 6f 7b 7b 76 700 700 700 700 write data ratios: 76 6f 78 77 1b3 2eb 292 51 write dqs ratios: 56 4f 58 57 193 2cb 272 31 leveling errors: -w- --- --- -w- fifo rst errors: 0 1 1 1 <<do_sdram_init() 4d000000 ### SDRAM: identified: 4 expected: 40000000 ###
U-Boot SPL 2016.11-00249-gcb460d33abe8 (Mar 07 2017 - 09:18:21) OMAP5432-GP ES2.0
sdram_init()
in_sdram = 0
do_sdram_init() 4c000000
omap5_ddr3_leveling(0x4c000000) ddr3 write leveling timeout ddr3 read dqs gate training timeout cmd phy dlls: ok f6 ok f6 data phy dlls: ok f9 ok f4 ok fc ok f7 phy status 5-7: c3 99990820 924 read dqs ratios: 7f 43 7f 3c 0 0 0 0 fifo we ratios: 0 7e 0 75 700 700 700 700 write data ratios: 10a 6e 10a 7a 26b 307 365 12 write dqs ratios: ea 4e ea 5a 24b 2e7 345 3f2 fifo misalignment: - yes - yes fifo rst errors: 15 3 15 1 cmd phy dlls: ok f6 ok f6 data phy dlls: ok f8 ok f4 ok fc ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 7e 43 7e 3c 0 0 0 0 fifo we ratios: 7ff 7d 7ff 74 700 700 700 700 write data ratios: 107 6d 103 77 26b 307 365 12 write dqs ratios: e7 4d e3 57 24b 2e7 345 3f2 leveling errors: r-- -w- r-- -w- fifo misalignment: yes - yes - fifo rst errors: 0 1 0 1 <<do_sdram_init() 4c000000
do_sdram_init() 4d000000
omap5_ddr3_leveling(0x4d000000) cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fb ok fb ok f4 phy status 5-7: 0 99990924 924 read dqs ratios: 3d 3b 38 46 0 0 0 0 fifo we ratios: 70 7b 7b 75 700 700 700 700 write data ratios: 78 72 7b 78 1a3 2eb 292 57 write dqs ratios: 58 52 5b 58 183 2cb 272 37 fifo misalignment: yes yes yes yes fifo rst errors: 1 1 2 2 cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fb ok fc ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3d 3b 38 46 0 0 0 0 fifo we ratios: 6f 7a 7a 74 700 700 700 700 write data ratios: 76 70 79 76 1a3 2eb 292 57 write dqs ratios: 56 50 59 56 183 2cb 272 37 leveling errors: --- rw- rw- --- fifo rst errors: 0 1 0 0 <<do_sdram_init() 4d000000 ### SDRAM: identified: 4 expected: 40000000 ###
U-Boot SPL 2016.11-00249-gcb460d33abe8 (Mar 07 2017 - 09:18:21) OMAP5432-GP ES2.0
sdram_init()
in_sdram = 0
do_sdram_init() 4c000000
omap5_ddr3_leveling(0x4c000000) cmd phy dlls: ok f7 ok f6 data phy dlls: ok f9 ok f4 ok fc ok f8 phy status 5-7: 0 99990924 924 read dqs ratios: 3f 46 39 3b 0 0 0 0 fifo we ratios: 68 7c 74 74 700 700 700 700 write data ratios: 76 6e 6f 7a 28b 30f 365 12 write dqs ratios: 56 4e 4f 5a 26b 2ef 345 3f2 fifo misalignment: yes yes yes yes fifo rst errors: 1 1 1 2 cmd phy dlls: ok f7 ok f6 data phy dlls: ok f8 ok f4 ok fc ok f7 phy status 5-7: 0 99990924 924 read dqs ratios: 3f 46 39 3c 0 0 0 0 fifo we ratios: 67 7b 73 73 700 700 700 700 write data ratios: 74 6c 6d 78 28b 30f 365 12 write dqs ratios: 54 4c 4d 58 26b 2ef 345 3f2 fifo rst errors: 1 1 1 1 <<do_sdram_init() 4c000000
do_sdram_init() 4d000000
omap5_ddr3_leveling(0x4d000000) cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fb ok fc ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3b 3b 37 46 0 0 0 0 fifo we ratios: 71 7c 7c 75 700 700 700 700 write data ratios: 78 71 7b 78 1bb 2eb 292 d1 write dqs ratios: 58 51 5b 58 19b 2cb 272 b1 fifo misalignment: yes yes yes yes fifo rst errors: 2 2 2 2 cmd phy dlls: ok f9 ok fc data phy dlls: ok f7 ok fc ok fc ok f3 phy status 5-7: 0 99990924 924 read dqs ratios: 3b 3b 37 46 0 0 0 0 fifo we ratios: 70 7b 7b 76 700 700 700 700 write data ratios: 75 6f 78 76 1bb 2eb 292 d1 write dqs ratios: 55 4f 58 56 19b 2cb 272 b1 leveling errors: --- --- --- -wg fifo misalignment: - - - yes fifo rst errors: 1 1 1 1 <<do_sdram_init() 4d000000 get_ram_size() successful <<sdram_init()
spl:board_init_r()
spl_init() Trying to boot from MMC1 Found LC15 V5.1 board_mmc_init for LC15 51 called gpio7 = eMMC gpio82 = 0 (mmc1=eMMC) gpio76 = 1 (ctrl=soft) spl: payload image: U-Boot 2016.11-00249-gcb460d33ab load addr: 0x807fffc0 size: 388720 Jumping to U-Boot loaded - jumping to U-Boot...
U-Boot 2016.11-00249-gcb460d33abe8 (Mar 07 2017 - 09:18:21 +0100)
CPU : ARM Cortex-A15 r2p2 SoC : OMAP5432-GP ES2.0 Model: Pyra-Handheld-V5.1 Board: Pyra with Letux Cortex 15 DRAM: >>sdram_init() 2 GiB Reset: peripherals tca642x@ 0x22 (24 pins): Bank 0 Configuration: iiiiiiii Polarity: 00000000 Input value: 00100000 Output value: 11111111 Bank 1 Configuration: iiiiiiii Polarity: 00000000 Input value: 01001000 Output value: 11111111 Bank 2 Configuration: iiiiiiii Polarity: 00000000 Input value: 00100010 Output value: 11111111 tca6424 init tca6424 initialized tca642x@ 0x22 (24 pins): Bank 0 Configuration: oooooooo Polarity: 00000000 Input value: 00000000 Output value: 00000000 Bank 1 Configuration: oiooiooo Polarity: 00000000 Input value: 01001000 Output value: 00000000 Bank 2 Configuration: ooooiiii Polarity: 00000000 Input value: 00000010 Output value: 00000000 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1, OMAP SD/MMC: 2, OMAP SD/MMC: 3 *** Warning - bad CRC, using default environment
Found LC15 V5.1 Found Pyra MB V5.1 Device Tree: omap5-letux-cortex15-v5.1+pyra-v5.1.dtb SCSI: SATA link 0 timeout. AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst scanning bus for devices... Found 0 device(s). Press SPACE to abort autoboot in 5 seconds =>
Matthijs