Re: faster mmc/sd

On 27 March 2017 at 07:20, H. Nikolaus Schaller hns@goldelico.com wrote:

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I think 92 MHz gets rounded down to 48 MHz and 144 MHz gets rounded down to 96 MHz.

Ah yes, that is well possible. And 192 MHz would stay 192 MHz.

Note that rounding this coarse really isn't necessary, but is probably due to sdhci: sdhci v2: power-of-two up to /256 sdhci v3: /1 or even divider up to /2046 omap-hsmmc: any divider up to /1023

So 192/3 = 64 MHz should really be available at least.

Moreover on the omap5, MMC1 and MMC2 (1-based) each has its own functional clock, selectable from { 64, 96, 128, 192 } MHz.

Wouldn't/shouldn't that round down be reported by cat /sys/kernel/debug/mmc0/ios ?

That would have been nice yes.