On 26 September 2017 at 12:41, Michael Mrozek EvilDragon@openpandora.org wrote:
Dual Die Input cap is more critical regarding writing.
Do they mean the power supply decoupling caps?
DLL Off means that the data will not be sent based on the clock...
Does the controller do an auto-training during power up?
Yup, which apparently suffices to compensate for the changes in read timing caused by DLL off. (Although possibly DLL-off timings might also be more prone to drift with temperature?)
With DLL off you should have a lot more issues than with DLL On... I've got no real explanation why a Dual Die should work better with DLL Off than on (except for if the timings aren't properly setup / trained).
I'm glad I'm not the only one puzzled by that.
A possibility could be that the termination is improper
The simulations juliano did seem to suggest signal integrity ought to be fine even without termination though.
A proper simulation with IBIS can only be done if the ODT Timings and values are known.
The values are known. I'm not 100% sure when exactly EMIF will assert the ODT signals though, I don't think I've ever seen this documented anywhere.
But if hardware leveling doesn't work with high temperatures, then it's probably more than just a bit of tuning...
Yup. To be fair, the hardware leveling done by EMIF has a history of being buggy and noise-sensitive. In earlier chips it was completely unusable and defeatured. On the other hand, I don't think I've ever seen a leveling failure on my 2GB cpu board, nor on the uEVM.
But if DLL off works better than DLL on, it certainly looks like a timing issue, not a termination issue.
Does DLL-off affect power consumption? (The simulation results for noise levels on VDD_DDR3 are still on my mind)
And Termination. That's probably a question for Nikolaus: What resistors do we have here - and could those easily be changed for testing on a CPU board?
There are no termination resistors other than those on-die (in omap and in memory). Discrete termination is normally only used for the command/address lines in a fly-by topology, whereas we're using a T-branch topology. See figure 7-48 "Floor Plan for the x16 DDR3 (T-Branch)" in section 7.7.2.4 "T-branch and Fly-by Topologies" of the OMAP5 public datasheet (SWPS051K).
Matthijs