Hi Tony, I have started to work a little on aess integration to latest mainline (i.e. once again try to reintegrate the old TI code) for omap5 (and later for arch/arm/boot/dts/omap4-l4-abe.dtsi).
At the moment I am stuck with properly setting up the ranges and reg translation for the AESS registers and memory.
I have based the DTS setup on the discussion on https://patchwork.ozlabs.org/project/devicetree-bindings/patch/2017083015195...
My current attempt to augment arch/arm/boot/dts/omap5-l4-abe.dtsi
target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0xf1000 0x4>, <0xf1010 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; /* CHECKME: OMAP4 and OMAP5 may differ in memory sizes */ ranges = <0xf1000 0xf1000 0x1000>, /* MPU private access */ <0x80000 0x80000 0x10000>, /* DMEM 64KiB - MPU */ <0xa0000 0xa0000 0x1000>, /* CMEM 4KiB - MPU */ <0xc0000 0xc0000 0x10000>, /* SMEM 64KiB - MPU */ <0xe0000 0xe0000 0x1fff>, /* PMEM ?KiB - MPU */ <0x490f1000 0x490f1000 0x1000>, /* L3 Interconnect */ <0x49080000 0x40180000 0x10000>, /* DMEM 64KiB - L3 */ <0x490a0000 0x401a0000 0x1000>, /* CMEM 4KiB - L3 */ <0x490ce000 0x401c0000 0x10000>, /* SMEM 64KiB - L3 */ <0x490e0000 0x401e0000 0x1fff>; /* PMEM ?KiB - L3 */
aess: aess { compatible = "ti,omap4-aess"; reg = <0x0 0x3ff>, /* MPU private access */ <0x80000 0xffff>, /* DMEM - MPU */ <0xa0000 0x1fff>, /* CMEM - MPU */ <0xc0000 0xffff>, /* SMEM - MPU */ <0xe0000 0x1fff>, /* PMEM - MPU */ <0x490f1000 0x3ff>, /* L3 Interconnect */ <0x49080000 0xffff>, /* DMEM - L3 */ <0x490a0000 0x1fff>, /* CMEM - L3 */ <0x490ce000 0xffff>, /* SMEM - L3 */ <0x490e0000 0x1fff>; /* PMEM - L3 */ reg-names = "mpu", "dmem", "cmem", "smem", "pmem", "dma", "dmem_dma", "cmem_dma", "smem_dma", "pmem_dma"; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; dmas = <&sdma 101>, <&sdma 102>, <&sdma 103>, <&sdma 104>, <&sdma 105>, <&sdma 106>, <&sdma 107>, <&sdma 108>; dma-names = "fifo0", "fifo1", "fifo2", "fifo3", "fifo4", "fifo5", "fifo6", "fifo7"; };
fails with that the first reg-names "mpu" reports OF_BAD_ADDR in __of_address_to_resource(). If I change the first ranges to <0x0 0xf1000 0x1000> this entry seems to succeed but the next one (for "dmem") fails. Therefore my aess driver doesn't successfully probe.
Since I am not that experienced with address translations, let me ask if you have an idea how to properly fix the mapping of DMEM, CMEM, SMEM to the aess child node.
BTW: having three disabled target-module nodes (@80000, @a0000, @c0000) for these MEM seems to be not necessary since these memory ranges are handled by the ti,omap4-aess driver through platform_get_resource_byname() during probe. I.e. there will be no separate user of these target modules to ever enable them.
BR and thanks, Nikolaus