With u-boot related memory errors out of the way fixed with patch "LC15: Fix flakey ddr3 detection with ref_ctrl and ref_ctrl_final", we can now narrow down the kernel related errors easily.
Playing with timing changes I narrowed down the kernel hangs to register sdram_tim3 where we need to increase the time for T_RFC. This is for "Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate, minus one" according to omap5432 TRM.
Maxing out the value for bits 12:4 made the new 4GB pyra's C02 and C03 boot reliably. And then looking at the timings again, the T_RFC value should be 187 - 1 (0xBA) and not 139 - 1 (0x8A). Note the Upper case B vs 8 :)
Value 187 - 1 (0xBA) matches Samsung K4B8G1646D-MYK0 datasheet "[ Table 34 ] Timing used for IDD and IDDQ Measured - Loop Patterns" for DDR3-1066 8Gb memory. We are currently using 4Gb value 139 - 1 (0x8A).
It is possible that this was caused by B vs 8 typo initially and then was not noticed because of the u-boot memory errors and getting confused with the memory datasheet for 4Gb vs 4GB while we have four 8Gb memory chips.
However I also noticed that value 187 - 1 (0xBA) still won't work reliably with new board C05. And new C21 and my older revision board C50 still did not work at all. However, using value of 191 - 1 (0xBE) makes all of them boot reliably for me. So let's use value 191 - 1 (0xBE) for now, and adjust it if needed based on testing with more pyras.
Note that we still can have pyra hang running two instances of memtester 1500M for about 10 minutes on bare CPU boards with no heat sink connected. The boards now boot reliably after that though, so presumably the pyra heat sink will solve this issue.
Signed-off-by: Tony Lindgren tony@atomide.com --- board/goldelico/letux-cortex15/lc15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -44,7 +44,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_2cs_es2 = { .ref_ctrl_final = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F88A8, + .sdram_tim3 = 0x027F8BE8, .read_idle_ctrl = 0x00050000, .zq_config = 0xD007190B, .temp_alert_config = 0x00000000,