On Thu 2018-05-17 06:59:49, H. Nikolaus Schaller wrote:
The register constants are so far defined in a way that they fit for the pcal9555a when shifted by the number of banks, i.e. are multiplied by 2 in the accessor function.
Now, the pcal6524 has 3 banks which means the relative offset is multiplied by 4 for the standard registers.
Simply applying the bit shift to the extended registers gives a wrong result, since the base offset is already included in the offset.
Therefore, we have to add code to the 24 bit accessor functions that adjusts the register number for these exended registers.
The formula finally used was developed and proposed by Andy Shevchenko andy.shevchenko@gmail.com.
Suggested-by: Andy Shevchenko andy.shevchenko@gmail.com Signed-off-by: H. Nikolaus Schaller hns@goldelico.com
drivers/gpio/gpio-pca953x.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index c682921d7019..4ad553f4e41f 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -222,9 +222,11 @@ static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) { int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
- int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
- int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
Is this reasonable to do on each register access? Compiler will not be able to optimize out fls and shifts, right?
Pavel