* Matthijs van Duin matthijsvanduin@gmail.com [170814 09:15]:
On 14 August 2017 at 18:10, Tony Lindgren tony@atomide.com wrote:
OK I trust you there. Weird that it works at all with just one chip select configured..
That makes no sense to me, I'd expect this config to result in the upper 2G being an alias of the lower 2G. Any chance it might just be working by accident because only a small portion of the memory is actually being used?
Yes totally. I continued trying to boil down the minimal changes and was running two instances of memtester 1500M with just the following changes:
1. smps6 set to 1.41V (0x61)
And the kernel also set to the same voltage in the dts. No idea what the voltage should be really at this point..
2. Termination changed to 0
So your original ddr3 config with just termination changed, no mem kernel command line option. I'm seeing hangs pretty easily with two instances of memtester 1500M running, and have not tested yet if what I had yesterday is any better. Patch below for reference.
I've noticed that if I wait 10 seconds with power completely off, booting to u-boot works more reliably. So there may be some temperature issue or a wait missing somewhere after register writes.
Later,
Tony
8< ---------------- --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -37,8 +37,8 @@ const struct omap_sysinfo sysinfo = { */
const struct emif_regs emif_regs_ddr3_532_mhz_2cs_es2 = { - .sdram_config_init = 0x61851B3A, - .sdram_config = 0x61851B3A, + .sdram_config_init = 0x60851B3A, + .sdram_config = 0x60851B3A, .sdram_config2 = 0x0, .ref_ctrl = 0x00001035, .sdram_tim1 = 0xCCCF36B3,