Am 10.11.2016 um 03:13 schrieb Michael Mrozek EvilDragon@openpandora.org:
Am Wed, 9 Nov 2016 21:37:52 +0100 hat "H. Nikolaus Schaller" hns@goldelico.com geschrieben:
Hi,
Good!
For me it's a disappointment as I thought that change could have been missed by the confusion of the board production being stopped.
Me too.
I had hoped it, but I didn't expect it... things have never been straightforward or easy with the Pandora or Pyra :(
Hm. Very good question! Here is a photo of the chip we have got in the newest production run:> Maybe we can read the speed from it?
Yes. According to that information it's Revision 2 of the OMAP5432, full speed, standard production run from a tray.
No prototype, even the latest revision and not limited to 1GHz.
Good.
BTW, here you can see the battery of decoupling capacitors around the OMAP. There are much less, but you also see that there are signal traces directly near them so adding more of them becomes difficult.
Hmm, from the picture it looks like there's still space on the right side of the OMAP (where there are ground planes).
That is what I mention: there is no space to connect them on copper.
Also, they look like there could be smaller capacitors available as well... so we could add more.
It also looks like we could manually solder a few capacitors together and add them there... so we could do some testing here.
3rd dimension i.e. stacking them.
But don't expect too much from connecting multiple capacitors in parallel.
There are recommendations that a single capacitor can be better than two or more in parallel. How many capacitors are used is an area of myths.
For example:
http://web.mst.edu/~jfan/slides/Archambeault1.pdf
He summarizes in ~100 pages: "Value of capacitance not important"
The problem: I don't even know if he is right. I can just believe he has done several years of research in this area.
The models are so much idealized that I don't know how to apply them to a real world designs where many signal connections have to be squeezed in as well. Especially with the limited tools we have.
Well, this is black magic...
Anyways this is an experiment that can be tested without a ne PCB layout. And, it is extremely unlikely that it makes things worse.
And doing it exactly as recommended (individual VIAs for every capacitor) is impossible. The 3 copper layers below the surface layer are for connecting the DRAM chips and there are also constraints how to route them. So we mix two set of design rules in this area.
Do we need Vias? I thought they would only be needed if the capacitors are on the other side of the PCB. Or do they need VIAs to connect to the ground plane on the other side?
Yes. And we need them to connect the power signals.
Are there THAT many traces for the DRAM chips so that no vias are possible anywhere there?
Yes.
We have three additional invisible layers of DRAM wires below the surface.
Just a rough estimate (I am too lazy to count them exactly):
16 address lines per chip, 16 data lines, ca. 16 control lines. Address lines are the same for two chips each.
So there is a total of ca. 150 wires from OMAP to the 4 DRAM chips. Plus proper power supply for the DRAM chips. And mixed with proper power supply to the OMAP. And other OMAP signals (like i2c, gpios).
Originally I thought that 8 PCB layers are enough for this. But adding some other signals (OMAP to connectors) wasn't possible to thread through the DRAM connections. Therefore we needed two more PCB layers.
Well, we could go to 12 or 14 layers to make such things a little easier but more costly. We live in a world of trade-offs...
BR, Nikolaus