On Tue, Apr 21, 2020 at 06:42:17PM +0200, Philipp Rossak wrote:
Hi,
On 21.04.20 13:21, Maxime Ripard wrote:
Hi,
On Tue, Apr 21, 2020 at 11:57:33AM +0200, Philipp Rossak wrote:
On 20.04.20 09:38, Maxime Ripard wrote:
Hi,
On Fri, Apr 17, 2020 at 02:09:06PM +0200, Philipp Rossak wrote:
> I'm a bit skeptical on that one since it doesn't even list the > interrupts connected to the GPU that the binding mandates.
I think he left it out for a future update. But best he comments himself.
I'm currently working on those bindings. They are now 90% done, but they are not finished till now. Currently there is some mainline support missing to add the full binding. The A83T and also the A31/A31s have a GPU Power Off Gating Register in the R_PRCM module, that is not supported right now in Mainline. The Register need to be written when the GPU is powered on and off.
@Maxime: I totally agree on your point that a demo needs to be provided before the related DTS patches should be provided. That's the reason why I added the gpu placeholder patches. Do you have an idea how a driver for the R_PRCM stuff can look like? I'm not that experienced with the clock driver framework.
It looks like a power-domain to me, so you'd rather plug that into the genpd framework.
I had a look on genpd and I'm not really sure if that fits.
It is basically some bit that verify that the clocks should be enabled or disabled.
No, it can do much more than that. It's a framework to control the SoCs power domains, so clocks might be a part of it, but most of the time it's going to be about powering up a particular device.
So I think I've found now the right piece of documentation and a driver that implements something similar [1].
So I will write a similar driver like linked above that only sets the right bits for A83T and A31/A31s. Do you think this is the right approach?
That sounds about right yes
Maxime