14 Aug
2017
14 Aug
'17
2:46 p.m.
On 14 August 2017 at 16:11, Tony Lindgren tony@atomide.com wrote:
Maybe bit 3 means two ranks per emif instance here?
Um, yes? All emif settings are per emif instance obviously (although both of them are configured the same).
On 14 August 2017 at 16:27, Tony Lindgren tony@atomide.com wrote:
The data sheet "3.2 Stacked / Dual - die DDR3 SDRAM x16 Ballout" seems show just one chip select per die?
That's why it's called "chip select".
One die per emif?
Four dies per emif. Each emif has two chip select lines (ranks), and moreover there are two 16-bit dual-rank ram devices side by side since each emif has a 32-bit data bus.
See figure 15-46 on page 3403 of the public TRM (SWPU249AF). Figure 7-48 on page 331 of the datasheet (SWPS051K) is also useful.