On Tue, Mar 07, 2017 at 11:19:53AM +0200, Tero Kristo wrote:
On 06/03/17 19:03, Tony Lindgren wrote:
Yup this is similar to what I recall seeing where the clocks don't always lock on reboot.
ok, I've gotten the locking failures too, and managed to get a snapshot of some registers after warm reset and compared them to cold reset.
Haven't faced this issue myself, but ABE is notorious for this kind of issues I recall, due to custom clocking setup for that specific DPLL. Are you tweaking the source of that DPLL?
No differences in dpll_abe refclk or other settings in CKGEN_PRM.
CM_ABE_CLKSTCTRL is showing clock activity for: DPLL_ABE_X2_CLK ABE_GICLK ABE_24M_GFCLK no other differences within the ABE_CM register block
dpll_abe control is requesting low-power idle-bypass, which is also the reset default. The differences are that the (reset insensitive) multiplier is set to 560, and the status register says: bit 0: 0 DPLL is not locked bits 1-3: 0 transient state bit 4: 1 DPLL has been initialized
Clearly it can't be good that the PLL is being observed in transient state. It seems the PLL is "stuck" somehow.
Note that this doesn't always seem to happen, often enough the status reports it is in "low power stop", same as after cold reset.
If I manage to catch it in this state again while in u-boot I'll see if I can unwedge it by meddling with registers. Suggestions are welcome.
Matthijs