* Matthijs van Duin matthijsvanduin@gmail.com [170817 07:56]:
On 17 August 2017 at 16:49, Matthijs van Duin matthijsvanduin@gmail.com wrote:
On 17 August 2017 at 15:38, Michael Mrozek EvilDragon@openpandora.org wrote:
- The timings are DIFFERENT when running with 400MHz (DDR3-800) and
often not in the datasheets.
The datasheet of the RAM does specify the timings to be used for DDR3-800, and we are using them. These timings are also the same as for the single-rank ram.
Ignore me, I wasn't awake yet. I was confusing the pyra with the beaglebone I think :-/
I think you can mostly get away with using DDR3-1066 parameters at 400 MHz, although it would unnecessarily slow. A few parameters need to be adjusted however, like the max time a row is allowed to be open (tRAS_max) and the refresh interval.
We have omap_ddr_clk() return 531840000 in u-boot, so not 400 MHz. But since the current timings work at 1.42V, I don't see why they would need to be tweaked for 1.35V.
Regards,
Tony