Hi Tony,
Am 16.10.2018 um 20:19 schrieb Tony Lindgren tony@atomide.com:
- Tony Lindgren tony@atomide.com [181016 18:04]:
I wonder if some of the ddr3 control signals could be crossed, or if some control signals need to be left out for emif2?
So here I'm thinking TRM "Figure 15-46. EMIF DDR3 Generic Configuration"
in my TRM (Version Y) there is Figure 16-48. EMIF DDR3 Generic Configuration.
that shows the lines that should be different for each die:
CK NCK ODT CKE NCS
So each emif has two chips with each chip having two dies. To me it seems Figure 15-46 matches how it should be?
Yes.
So the signals listed above should be selectively connected for each chip in the emif and not to both chips on the emif?
I have checked the schematics and there are for each dual-die chip:
CK (common to both dies) NCK (common to both dies) ODT0, ODT1 (individual for each die) CKE0, CKE1 (individual for each die) NCS0, NCS1 (individual for each die)
Which means both dies share the same clock but have the other controls separately.
EMIF provides CKA, NCKA, CKB and NCKB. The first two are connected to CK, NCK and the other two are not connected. We can't connect (N)CKB anywhere because the dual-die chips have no separate clock inputs...
This would mean the EMIF must be programmed in a way that takes care of this shared clocks...
Hm. Could it be that the configuration assumes clka and clkb being enabled/disabled separately for self-refresh. And then for example clka is stopped? Which also stops the clock of cke1 die which isn't expected by the EMIF?
BR, Nikolaus