At 21:11 +0200 on Monday 2017-09-18, Matthijs van Duin wrote:
The memory is binned for CL=7 @ 533 MHz, which means the manufacturer guarantees those timings.
True. But on the actual hardware as built, has the 532 MHz memory bus clock been measured to be sufficiently accurate and sufficiently stable that it doesn't exceed 533-1/3 MHz?
Of course lowering the clock frequency could nevertheless be beneficial since gives all nets (both signal and power) more time to stabilize again after a transition. Doing so however would require lowering the frequency of the core PLL and thereby all clocks that derive from it (which include all interconnects and the GPU), which would be annoying from a performance point of view.
Indeed. But in the surprising event that this did turn out to be the problem, such a drastic reduction as going down to 507 MHz might not be needed -- perhaps 520 MHz or 525 MHz would work, which wouldn't be quite such a horrible performance hit.
I'm also fairly sure that CL is only relevant for timing closure internal to the memory, hence increasing it won't fix issues with the interfacing between memory and omap.
Well if the board and the processor do support a memory bus clock speed in the next faster bin (with CL = 9, CWL = 7 etc.), it might be worth checking/testing this at least -- provided that more promising avenues for testing do not occupy all the available time, of course.
N.