On 14 August 2017 at 06:39, Tony Lindgren tony@atomide.com wrote:
- Configure smps6 to 1.39V instead of 1.35V
So what does this mean? Not enough power from palmas or too low voltage for the 4GB DDR3 chip? Any ideas?
One thought that crossed my mind is that the 60Ω termination value configured in the ram might be inappropriate with two ranks. This value is configured in bits 24-26 of sdram_config: 0 = no termination 2 = 120Ω 1 = 60Ω
I think it would be worth testing 120Ω termination or even no termination at all (this should work if the drive strength on the omap side matches the traces to ram, and would reduce power consumption).
The 4GB DDR3 datasheet says "1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)", so maybe we need to configure it to 1.35V separately somehow?
No
- Configure interleaving
Not sure if this is mandatory but needed for now it seems.
It is desirable for performance.
- Use igepv5 ddr3 timings instead of Matthijs' timings
Have not checked what's different.. I'll post my WIP patches shortly and let's figure it out, maybe Matthijs can spot the differences :)
I think I checked what igep did, but I can take another look.
AFAIK, there is a DRA7 tool to calculate some EMIF parameter block which takes wire lengths from SoC to DDR3 into account. The EMIF seems to be able to add some picoseconds here and there...
That's determined automatically using hw leveling. The ram issue has however often manifested itself as a hw leveling failure, since it's a bit sensitive to noise and such.
Matthijs