Hi,
Am 15.12.2016 um 00:59 schrieb Andreas Lausch andreas@flausch.at:
On 2016-12-14 17:53, H. Nikolaus Schaller wrote:
Copper foil thickness is defined in a build-up spec by you or the manufacturer.
What we don't know is if these Chinese do what has been agreed on :)
I'd give them more credit ;) They try to minimize costs on gold (by using exactly 1 atom thick layer of gold) but most of them try their best on anything else. Since copper is washed out, they probably have pre-foiled FR4 which is "level enough" to pass any E-test after laminating multi layer PCBs.
Well, we just do not know.
[Impedance calculation] It sounds like a typical service different PCBs designers would use. Not something specifically bound to a design.
It's easier to do this from source files than from gerber (because gerber does not specify the layer stack), so "good" pcb design tools integrate this to some extend
AFAIK Altium has started to have something but high end tools have it for a long time.
Even Protel (DXP) 98 has "signal integrity", maybe even with "simulation". But I never tried any simulation options with something else than Altium DXP 2008ish in school and that was with ideal components, iirc.
Well, getting access to such a tool is one side. The other is someone really working with it. It would be new for us all and we are not only financial budget limited but also time.
Yeah, that's something that only works if you know someone who knows someone; university part was more like an open suggestion to the ML.
Exactly. We mainly lack really experienced manpower in one very special area.
3rd dimension i.e. stacking them. But don't expect too much from connecting multiple capacitors in parallel. There are recommendations that a single capacitor can be better than two
Imho, the only reason that single caps are better than multiple caps is that they can be "tighter" (no copper and no casing between two caps).
Yes, that is what I also think. Adding more capacitors doesn't help much (usually - there are some exceptions).
There is of course another effect. A 10uF is "invisible" for high frequencies. So connecting a 10pF in parallel increases decoupling for very high frequencies.
That's not true. For 1 GHz AC _signal_, the "pure" 10µF capacitor is 16µOhm, the 10pF is 16Ohms against ground. So a "bigger" cap is better to "short" noise to ground. That calculation is for EMI. For decoupling it's better to think about the voltage drop inside the cap: dV=(I*t)/C, which is also better with bigger caps. The problem with big caps is the actual capacity (in regard to applied DC and temperature) as well as the ESR (in regard to capacity and temperature). At 25°C, 1GHz, similar package, 1nF NP0 may have a similar ESR to 100nF *7R and that may have a similar ESR to 10µF X5R which may be around 0.1 Ohms. Higher voltage types *may* have a higher ESR because of layout (see datasheet). (The 10µF cap from above has 0.1Ohms against GND, not 16µOhms. The 10pF one has 16.1Ohms).
I have done that a while ago but there was no clear result because it wasn't done systematically. Maybe I should repeat with latest knowledge about different kernel OPPs and if it depends on CPU load.
Anyway. If you've tried stacking one or two caps (esp. something like 100nF X7R @ 16V) without any noticeable difference, that's probably not a solution. The ESR would be <50%.
Power planes and power traces (may) have a defined return path parallel to it, so there is not only the copper's L but also the board's C across the FR4, which defines the impedance. Vias don't have that. So, to reduce the inductance of vias by half, you just place twice as many. (Note: It's hard to route good-enough impedance-matched traces with vias without special tools (-> read docs, trial and error; been there, done that)).
And we are in the middle of that situation... No special tools but a problem.
Not exactly. You want to reduce the impedance to a minimum, not match it to sink/source. The capacity between VDD and GND (plane) may help at those frequencies; anything about that (physical rounting of VCC vs. GND) in the docs?
Only general rules: keep as close as possible, minimize, ... And the hint to use high-end tools.
- the problem seems to appear as soon as VDD-MPU rises above ca. 1150mV and higher load - a little weaker at 1GHz and more significant >1.25GHz
What's the rated voltage of the caps ?
Well, we have not specified them precisely. But I assume X5R and 6V. And they are operated at ~1.1V (1.25V max.).
Or better: have you compared your caps' C and ESR at maximum applied DC voltage to the reference design's caps? The 0.1Ohm X5R from above has only 5µF at 30% rated voltage (1µF at 100%) and a similar cap with rated voltage x4 (25V) has 10Ohm at 1GHz.
I can try to find out which model was chosen.
But it does not obviously explain the sudden increase of problems between 1.1V and 1.15V (quite independent of clock frequency).
So I am starting to believe that it is not decoupling of VDD-MPU but maybe too much overall GND noise (which significantly grows with voltage and CPU clock and load).
Well... impedance has to be viewed from source to sink, which includes GND, but if the noise on GND is the same across all GND pins and the decoupling of VDD,PLL is good enough, that should make no difference; BUT I'd strongly recommend to try to follow reference design's instruction on GND connection and I'd try to make GNDs inductance way smaller than VDDs inductance.
The new pcb layout goes in this direction - but I have no idea how far and if it is enough.
Which makes the oscillator/PLL fail.
It would be really nice to pin it on that. Some PLLs seem to be very sensitive, others are not. (Never worked above 1GHz though). Is there any way to have PLL/Div on a pin to see if the PLL fails or is there a fault condition for failed PLL (checking would probably require jtag)?
Yes, it could be possible to find by JTAG. The good news is that it is possible to enable JTAG on the SD slot pins after boot so that we just need to boot from eMMC with a special version of U-Boot and an adapter.
Plus manpower with someone experienced who has JTAG equipment waiting for just another task.
Especially as looking into the real PCB layout has shown that we have just 4 VIAs for the whole GND connection and there is room for more. So this has already been updated for the next CPU-PCB - but we don't know if it is effective until we build some (which is very very expensive - you almost get a small car for it and ED grey hair).
For some manufacturers you have to pay for a fixed-size production panel, regardless of resulting PCB count, if it can't/won't be pooled. When inquiring I'd ask the supplier about that. (A live inquire at euro circuits shows a price difference of EUR 60 out of EUR 2000 for 1 PCB vs. 75 PCBs.)
Yes, that is normal. But 1 of our PCBs is even more than 2000 EUR. We also have to add pick&place setup cost and one full day renting the fab. Just for a single CPU board (or panel of 6).
By the way, not sure what you pay for PCBs, but we use Euro circuits for prototypes because they are pretty fast (and not that expensive). For 1 production panel (or pooling of samples, if applicable), standard service is 7 working days, regardless of layer count. Most of the time they use CNC laser exposure on photo resist, so you wont pay any fixed costs for films (per layer).
We need 12 layers with laser drills. This can not be pooled.
As a next step we have planned to remove decoupling caps from an OMAP5432EVM to see if they are really necessary for 1.5GHz operation. For that I am waiting to receive an OMAP5432EVM that is no longer needed - since if it fails it might not be possible to repair.
For me, that's the best idea of 2016. Never would've thought of that.
:)
Best Regards Andreas Lausch a.k.a. Black Sliver
Probably the best help would be if ED can give you a prototype (as soon as the new main&display boards have been built - and if he has a spare one) so that you can do measurements and experiments in parallel to me.
I'd be happy to help, but I'm pretty sure I have zero non-occupied after-work-free-time until end of the year (mainly because of work).
Same as for everyone :(
Well, looking at the calendar: beginning of next year would suffice :)
Best regards and my respect for the work done so far
Thanks and BR, Nikolaus