Hi,
since TrashyMG from the forums asked me to join the ML after posting this, I did.
https://pyra-handheld.com/boards/threads/prototype-mainboards-coming-soon.78...
So, my thoughts on that topic:
Well, we can estimate. If the core draws 5A peak current I would say the 1.25V should not change by more than 0.05V. This means < 10 mOhm. A rough estimate for standard copper traces on such PCBs is (I hope they did not make them thinner):
Copper foil thickness is defined in a build-up spec by you or the manufacturer.
1cm wire 100μm wide means 50 mOhm. So 500μm wide and 1cm long means 10mOhm. We might have 2cm... But all this is rough guess.
But that's just valid for DC which is not a real problem, since the DC/DC converter measures the voltage inside the SoC as far as I read.
[Impedance calculation] It sounds like a typical service different PCBs designers would use. Not something specifically bound to a design.
It's easier to do this from source files than from gerber (because gerber does not specify the layer stack), so "good" pcb design tools integrate this to some extend, which reduces the need for specialized tools/services. Anyway, afaik there ARE some stand-alone tools, but owners of such tools are into electronics development as well (the bad guys that want to sell you finished designs). You could maybe try to find a university that uses such tools in courses? Maybe TüV has access to such tools (because impedance calculation is also relevant for EMI)?
3rd dimension i.e. stacking them. But don't expect too much from connecting multiple capacitors in
parallel.
There are recommendations that a single capacitor can be better than two
Imho, the only reason that single caps are better than multiple caps is that they can be "tighter" (no copper and no casing between two caps).
or more in parallel. How many capacitors are used is an area of myths.
Using two caps halves the ESR, but you could as well use a bigger cap with half the ESR. The reason for 2x10µF (instead of a "better" 1x22µF with equal voltage and dielectric) is often just the availability in the recommended package.
For example: http://web.mst.edu/~jfan/slides/Archambeault1.pdf He summarizes in ~100 pages: "Value of capacitance not important"
See the forums link above.
Is it the OVERALL power consumption that causes a problem or just peaks?
The ripple caused by overall power consumption can be measured using a scope across caps.
Maybe we can make the PALMAS react less aggressive, so that it doesn't increase the voltage suddenly (leading to peaks) but in lower steps?
Don't know about the exact switching frequency, but it's definitely way slower than the SoC and bulk caps should "eat" ripples at those frequencies.
[vias]
Power planes and power traces (may) have a defined return path parallel to it, so there is not only the copper's L but also the board's C across the FR4, which defines the impedance. Vias don't have that. So, to reduce the inductance of vias by half, you just place twice as many. (Note: It's hard to route good-enough impedance-matched traces with vias without special tools (-> read docs, trial and error; been there, done that)).
[separate vias]
having a via per pin will move (most) of the pin's current to the "closest" via, which may or may not further reduce voltage drops.
[jtag]
It would be interesting to see what parts of the SoC are still alive to better guess the cause. But for some SoCs that may not work at all; NXP's cortex M4s may completely freeze on some hard faults, not even answering to jtag.
Best Regards Andreas Lausch a.k.a. Black Sliver