On Tue, Nov 22, 2016 at 10:49 PM, H. Nikolaus Schaller hns@goldelico.com wrote:
- it shows that the thermal throttling makes clock OPP go down to 750/500 MHz, sometimes in multiple steps
Hmm still using those TI unsupported low frequencies? I'd drop them just in case they have some problem, they must have had a reason to remove it from mainline.
Also the latest datasheet (swps051k) lists 1.014V as the lowest allowed voltage, I'd not ever go below that in tests like this as you may end up triggering several unrelated issues and then arrive to wrong conclusions.
- since this OPP change also includes VDD-MPU changes (between 1.25V and 0.85V) it shows that the Palmas regulation works fine
- what makes a really big difference is running the bash-loop vs. the NEON-loop
- high-load freezes almost immediately after switching from 1GHz to 1.25GHz
What about 1.2GHz? ED already announced 1.2GHz as fully working on the forums, but I fear it might actually not work with NEON.
- it is indeed the Cortex A15 MPU/NEON core and not any peripheral on the OMAP5 SoC A weird reason could still be that the DRAM interface is used differently/faster if we run NEON at >1GHz. But the EMIF DRAM clock is constant if CPU clock changes.
The test doesn't use memory at all, it operates on registers only, except repeatedly reading and writing to the same locations, which should always hit L1 cache.
OTOH now that I think about it, it might actually start doing writes after a task switch because ARM doesn't write-allocate cache. You can comment out lines with ldrd and strd instructions (add @ at the start of lines 24 and 29) and then there will be no chance for it to do RAM accesses, except kernel reloading the instructions after a task switch (after interrupts or whatever). This should rule out any RAM issue.
GraÅžvydas