small update:
Am 10.11.2016 um 14:50 schrieb H. Nikolaus Schaller hns@goldelico.com:
Hi,
- VDD-MPU and GND resistance between Palmas and OMAP is <0.3 Ohmm
(my Multimeters are not more precise)
Not sure what the maximum allowed value is. :)
Well, we can estimate. If the core draws 5A peak current I would say the 1.25V should not change by more than 0.05V. This means < 10 mOhm.
A rough estimate for standard copper traces on such PCBs is (I hope they did not make them thinner):
1cm wire 100µm wide means 50 mOhm.
So 500µm wide and 1cm long means 10mOhm. We might have 2cm...
But all this is rough guess.
So we might have 20mOhm here? And we need < 10mOhm?
Or did I understand something wrong?
(Yes, I know it's just an estimation)
It is an estimation of what we have, not what we certainly need.
Now I have finished some real measurements.
What I did was to connect a power supply with current limitation control (set to 1 Ampere) right to the tips of a millivoltmeter.
And use the tips to short circuit some copper traces.
A reference resistor of 10 mOhm did show ~13mV while connecting the tips directly showed ~3mV. This means 10 mV difference at 1A and is indeed 10 mOhms.
Next, I measured between several contact pads on the naked CPU board (already converted into Ohms):
Palmas-GND - twl6040-GND ca. 4 mOhm Palmas GND - OMAP-GND ca. 4 mOhm
(SMPS measured at the inductor output):
Palmas-SMPS1 - OMAP-VDD-MPU ca. 12 mOhm Palmas-SMPS3 - OMAP-VDD-MPU ca. 9 mOhm
So this looks like being almost exactly the rough estimate I had written previously.
Interestingly I did have approx. 7.5 mOhm between Palmas-SMPS1 and Palmas-SMPS3 although they are quite close to each other. They are connected by 2 VIAs and one short copper trace. So the resistance of the VIAs is higher (ca. 2-3 mOhm) than I would have expected.
This means adding more VIAs here does not harm, could but also might not solve any problem we have. At least it can not introduce new problems.
Also interesting was the measured resistance between two almost adjacent BGA pads of the OMAP. There was 4mOhms as well. But dependent on how much I pressed on the PCB.
So my needles have some influence on the results and the real resistance might be lower. On the other hand the BGA balls also have some resistance so this might properly model the measurements inside the OMAP.
A real problem has shown up for the connection of the new (wasn't in the first CPU boards) capacitor for VDD-MMU where you proposed to play with the values. This one shows approx. 33 mOhms. Together with 10 µF it makes a limit frequency in the low MHz range.
In other words: this capacitor has no decoupling effect at all. This might explain why we have no improvement @ 1.5GHz - if the capacitor theory is right.
Conclusions
=> series resistance of GND from Palmas to OMAP seems to be low enough => series resistance of VDD-MPU from Palmas to OMAP seems to be low enough => e.g. 3 A difference makes 3-4 mV difference of VDD-MPU and 1.2mV on GND => this is smaller than how precise we can set the OPP voltages => the resistance is IMHO in green range => anyways, it would be good if the VIAs would have lower resistance => put on to-do list for mass production revision => the additional capacitor could have been connected at a much lower resistance because it has a too small trace width - although there had been space in the innermost layers. It was a very late addition done in a hurry, obviously not thinking about it enough. => changing this value will not show any effect at high speeds :(
I have tried to bridge the weak wire to the capacitor with an external wire.
Unfortunately there is as expected no visible difference (well, this statistics isn't very precise due to small sample size). But as before it did come to login: in 2 out of 10 attempts and stuck in 8 of 10 (@1.25 GHz OPP enabled).
Then I made another observation which makes me believe a little more in a SW issue again:
If the kernel freezes, it is always between 6 and 10 seconds kernel time (@1.25 GHz).
Never before and never after this.
If the kernel runs successfully for 10 seconds, the boot process completes and after ~30 seconds we have a login: prompt.
This 6-10 seconds windows is for 30 boot attempts where a total of 7 did succeed.
Now I really wonder what the kernel doing in this time frame which can make it freeze here but not outside this window?
Some interrupt initialization? Waiting during a spinlock for some wrong address to have a specific state?
In addition we know that clock initialization and switching from U-Boot speed (1GHz) happens at ca. 3 seconds. That is where 1.5 GHz freezes.
Anyone with other ideas?
Or explanations for this effect (immediate crash @3 seconds @1.5GHz, freeze never between 3 and 6 seconds or after 10 seconds @1.25GHz)?
BR, Nikolaus
PS: is it possible to run U-Boot @ 1.5GHz?