Am 26.09.2017 um 15:25 schrieb Matthijs van Duin matthijsvanduin@gmail.com:
On 26 September 2017 at 12:41, Michael Mrozek EvilDragon@openpandora.org wrote:
Dual Die Input cap is more critical regarding writing.
Do they mean the power supply decoupling caps?
from context I think they refer to the capacity of each input (not power) pin (address, cs, data etc.) because that is the sum of two dies. Plus what the bonding wires can add. Our decoupling caps do not change.
This means we must drive more current into the wires so that these capacitors are charged/discharged faster. Or if we don't, they have a slower slope. Which means that the switching point from 0 to 1 or 1 to 0 is delayed in comparison to a single die ram package. Hence some signals arrive later.
What we don't know how big this effect is and which situation is really influenced.
And if *all* signals are slowed down y the same effect, it should compensate. Unless 0101 sequences become too fast. But we are far below max. RAM speed.
Apropos bonding: there could be more cross-talk inside the MCP than outside. I have no idea how these chips look like inside...
BTW: I have received another set of IM8G memory chip samples today and I hope I find time tomorrow to try to rework another CPU board.
Please cross fingers that the outcome is better and not another broken board (the one done previously has developed a short circuit on VDD-CORE which appears to be under or inside the OMAP5).
Otherwise we have to ask pick&place to build a handful of new CPU boards with these chips (eating more money and time).
BR, Nikolaus