As reported by Michael Mrozek, Pyra 4GB seems to hang quite easily within about 10 to 15 minutes when left idle, and it seems to be related to DDR3 self-refresh.
Setting DYN_ODT bits [22:21] enables ODT. Presumably there is one bit per rank or chip select. According to the TRM, we want to keep both bits cleared. And we want to configure DDR_TERM bits [26:24] to 3 which according to the TRM makes it RZQ/6. Trying to boot with DDR_TERM set to 2 won't work.
Additionally we also want to clear EMIF1_PHY_RD_LOCAL_ODT bits [6:5] in CONTROL_EMIF1_SDRAM_CONFIG_EXT to disable ODT further. And the same for CONTROL_EMIF2_SDRAM_CONFIG_EXT register. And we can just drop the unused define for SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2.
Note that the wiring for ODT0 and ODT1 should also be checked in the hardware. It seems that ODT0 must only be connected to the banks in the first rank only, and ODT1 must only be connected to the banks in the second rank.
I came across this information while search for DYN_ODT info, see a related KeyStone thread at [0] below. It says:
"ODT0 must be routed to all SDRAMs in the first rank. In dual-rank designs, ODT1 must be routed to all SDRAMS in the second rank. In designs with only one rank, ODT1 will be left unconnected."
It seems we now have ODT0 and ODT1 both connected to all banks on Pyra? I and I wonder if that might be the reason for TRM saying not supported for DYN_ODT?
Anyways, with ODT disabled, these signals should not do anything and fixing the hardware can probably wait.
[0] https://e2e.ti.com/support/processors/f/791/t/450668?DDR3-Dynamic-ODT-on-C66...
Reported-by: Michael Mrozek EvilDragon@openpandora.org Signed-off-by: Tony Lindgren tony@atomide.com ---
Only lightly tested so far, but my Pyra 4GB has survived now for more than 15 minutes :) Please test on multiple devices.. No need for the "disable internal DLL hack" with this any longer.
--- arch/arm/cpu/armv7/omap5/hw_data.c | 4 ++-- arch/arm/include/asm/emif.h | 3 ++- board/goldelico/letux-cortex15/lc15.c | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -661,8 +661,8 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = { .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, - .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, + .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_NO_ODT_11_SAMPLES, + .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_NO_ODT_4_SAMPLES, };
const struct ctrl_ioregs ioregs_dra7xx_es1 = { diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -538,7 +538,8 @@
#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 -#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7 +#define SDRAM_CONFIG_EXT_NO_ODT_11_SAMPLES 0x0000C187 +#define SDRAM_CONFIG_EXT_NO_ODT_4_SAMPLES 0x00000187
/* DMM */ #define DMM_BASE 0x4E000040 diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -42,7 +42,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_2cs_es2 = { .sdram_config2 = 0x0, .ref_ctrl = 0x000040F1, .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, + .sdram_tim1 = 0xCB8F36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F8BE8, .read_idle_ctrl = 0x00050000,