HI,
Am 31.08.2017 um 20:02 schrieb Michael Mrozek EvilDragon@openpandora.org:
On Do, 2017-08-31 at 17:30 +0200, H. Nikolaus Schaller wrote:
Hi,
Now I have done that and capacitors have not changed since the first CPU board prototype.
Ah, okay.
As it works for Tony if he increases the voltage and Juliano showed that we might have too much noise, then a LITTLE improvement might already be enough. So those >3 per DDR3 could help!
Yes, according to this completely unproven theory. I just want to say that I would prefer new facts before drawing conclusions from hypotheses :) I understand that you prefer to really do something than still be digging in the fog/mist.
Unfortunately it is hardware and not changing some line in source code and recompiling :(
I know, that's why I asked in my first mail whether someone has an idea what we could still check. What doesn't make sense is when no one tries anything in software anymore because there are no new ideas or everything has been tried already.
That would be a total standstill for hard- and software and that's worst case scenario.
Especially since changes cost money. >3 per DDR3 chip means:
- scrapping the 500 boards and
- trying to squeeze in more capacitors
- have PCBs built and populated
If it helps: fine. If not: wasted money and time.
Yep, I know. Scrapping the 500 boards would only make sense if it turns out to be the issue though. And if it IS the issue, then scrapping them would be the right thing to do.
But if no one knows another solution to try in software and nothing happens for about 8 weeks, we would have the time to build new PCBs.
So sure, finding a software solution is the highest priority, but if there are no ideas left we can't just sit and do nothign.
The change-compile-boot-analyse cycle for software is significantly faster...
I am well aware of that. But if you tinker around for 8 weeks and find out nothing helps, you still lost 8 weeks.
If you try to improve the PCBs and order a prototype sample, you can still tinker around. If you find the solution: Great! If you don't, at least you don't have to wait another 6 weeks for an improved PCB.
So yes, as long as there are more ideas and things to try, I don't want to try to fix the hardware. But once all ideas have been tried out, I don't want to waste any time either.
So I'd prefer to get more facts about different parameter sets that work/don't work etc. first.
Well, according to the distributor, they should work with standard Jedec timings without any issues. Same as the 2GB RAM.
If they don't, then they suggest to fix the hardware.
If we know what to fix, it is easy. But we don't even know what to fix in the hardware. The simulations did not reveal a problem so far.
And that additional capacitors may help is just a theory.
You remember: we had the same problem with the 2 GB RAM and >1.25 GHz OPPs and also discussed capacitors.
I even added some more capacitors on the backside of one PCB through scratching open some VIAs. It did not have any noticeable effect.
What did have a big effect - even without any additional capacitors - was to change the EMIF setup...
I'm fine if we use non-standard timings, of course (as long as it works), but according to the distributor, there shouldn't be much to setup in software, which is my biggest concern.
I don't understand the EMIF and DDR3 timings well enough to know what and if it can be improved by EMIF configs (I do not even understand in detail what the 2 GB patch really did).
BTW: higher voltage could also mean that the chips simply draw more current and we have more mV of voltage drop between Palmas output and DDR3L VDD input. This SMPS does not have a separate sense line going back from the DDR3L to the Palmas. It simply regulates the Palmas output to 1.35V. The voltage at the chip VDD pins be smaller. Hence we must configure the Palmas to send more. And dual-die chips need twice the current so the mV drop is twice as large... But on the other hand the chips are not selected both at the same time. So they are alternatingly active. Which means power consumption should not be twice as high.
Could be - but that is again speculation unless we can measure it somehow and demonstrate that this is the problem. If it is, we have two choices: a) make the wires from Palmas to DDR3L bigger (change PCB layout) b) set the Palmas to 1.42V so that the DDR3L gets 1.35V and keep the PCB as it is
To be honest, I don't feel that I have enough information to suggest either.
Hm. What we could ask is for the Samsung DDR3L single-die variant. I.e. same die, same package but only 2 GB in total. And rework one CPU board with those and compare to a 2 GB board with IM DDR3L 2 GB chip.
Or we can ask if IM has a 4 GB dual-die variant.
Would be a little risky transplantation, but then we know if it is IM vs. SAMSUNG or 2GB vs. 4GB. Nevertheless I would do such HW mods only after we are sure that all EMIF config options have been tried without success.
BR, Nikolaus