Based on igepv5 u-boot commit 4521f304a913 ("IGEPv5: Modify lisa_regs structure, added ma_hm_interleave variable") by Manel Caro mcaro@iseebcn.com, we need to configure interleaving for 4GB DDR3 to work properly. --- arch/arm/cpu/armv7/omap-common/emif-common.c | 5 +++++ arch/arm/include/asm/emif.h | 1 + board/goldelico/letux-cortex15/lc15.c | 14 ++++++++++++++ 3 files changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1339,6 +1339,11 @@ void dmm_init(u32 base) &hw_lisa_map_regs->dmm_lisa_map_0);
setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); + + /* MA_PRIORITY[8] HIMEM_INTERLEAVE_UN bit to 0x1 */ + if (lisa_map_regs->is_ma_hm_interleave) + __raw_writel(__raw_readl(MA_PRIORITY) | + (1 << 8) , MA_PRIORITY); }
/* diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -756,6 +756,7 @@ struct dmm_lisa_map_regs { u32 dmm_lisa_map_2; u32 dmm_lisa_map_3; u8 is_ma_present; + u8 is_ma_hm_interleave; };
#define CS0 0 diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -78,6 +78,20 @@ void dram_init_banksize(void) /* report 4 GB during boot */ gd->ram_size = gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size; } + +const struct dmm_lisa_map_regs lisa_map_pyra_4g = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80740300, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1, + .is_ma_hm_interleave = 0x1, +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &lisa_map_pyra_4g; +} #endif
/*