* Tony Lindgren tony@atomide.com [170907 08:42]:
Below is a more minimal version that just disables internal DLL on init. No idea why that helps, but it seems to be some kind of self-refresh clocking configuration issue.
Looks like we never write .sdram_config though? In that case this version is no different and internal DLL stays disabled.
Regards,
Tony
8< ------------------- From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren tony@atomide.com Date: Wed, 6 Sep 2017 21:42:01 -0700 Subject: [PATCH] Pyra/LC15: Disable DDR3 internall DLL to get 4GB working
I was wondering about the weird non-sensical 0xffff ref_ctrl and was thinking maybe we have multiple clocks going? And by setting ref_ctrl to 0xffff we stop their interaction for most part and this allowed me to boot kernel and run memtester..
Anyways, setting bit 20 to disable DDR3 internal DLL allowed me to remove the weird non-sensical 0xffff value for ref_ctrl. And further testing showed that this also allows removing the rest of the hacks as well and I can run two instances of memtester 1900M with Matthij's timings!
And from there we get to the point where the internal DLL only needs to be disabled for .sdram_config_init.
Note that the board needs to be let cool down before booting, otherwise you can get the "dq test failed" errors in u-boot.
board/goldelico/letux-cortex15/lc15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/goldelico/letux-cortex15/lc15.c b/board/goldelico/letux-cortex15/lc15.c --- a/board/goldelico/letux-cortex15/lc15.c +++ b/board/goldelico/letux-cortex15/lc15.c @@ -37,7 +37,7 @@ const struct omap_sysinfo sysinfo = { */
const struct emif_regs emif_regs_ddr3_532_mhz_2cs_es2 = {
- .sdram_config_init = 0x61851B3A,
- .sdram_config_init = 0x61951B3A, .sdram_config = 0x61851B3A, .sdram_config2 = 0x0, .ref_ctrl = 0x00001035,
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