On 18 September 2017 at 20:04, N. Jackson nljlistbox2@gmail.com wrote:
At 06:03 +0200 on Monday 2017-09-18, Matthijs van Duin wrote:
For our memory that's the DDR3-1066F bin, which means it supports 7-7-7 timings (which we're using).
Does the memory bus clock need to run so fast, so close to the maximum for the bin?
With CL = 7 the range is (400, 533 1/3] MHz according to the K4B8G1646D datasheet. 532 MHz seems very close to the top edge.
What happens if you back it off 5% from the bin edge and run the clock at 507 MHz or so?
The memory is binned for CL=7 @ 533 MHz, which means the manufacturer guarantees those timings. I'm also fairly sure that CL is only relevant for timing closure internal to the memory, hence increasing it won't fix issues with the interfacing between memory and omap.
Of course lowering the clock frequency could nevertheless be beneficial since gives all nets (both signal and power) more time to stabilize again after a transition. Doing so however would require lowering the frequency of the core PLL and thereby all clocks that derive from it (which include all interconnects and the GPU), which would be annoying from a performance point of view.
Matthijs