On 28 August 2017 at 17:27, H. Nikolaus Schaller hns@goldelico.com wrote:
In other words: higher driver strength sends stronger signals and this charges/discharges capacitors formed by the Si chips in the DDR3 Multi Chip package faster. Faster charge/discharge gives better signals (usually) and more room for timing misalignment.
Well... this description is only accurate if the propagation delay (trace length) is negligible in comparison to the rise/fall time. In general, drive strength can also be too high and result in overshoot.
But it looks as if Tony, Juliano and Matthijs have already discussed that.
Signal integrity simulation based on IBIS data of the omap5 and ram show very clean eye diagrams, not only for the default ODT setting (60Ω) but even if ODT is disabled (to reduce consumption and increase voltage swing). Based on this it seems the default drive strength (40Ω) should be fine.
Matthijs